Search Results - "QI, Jieming" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology

A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology

by Gangasani, G. R., Chun-Ming Hsu, Bulzacchelli, J. F., Rylov, S., Beukema, T., Freitas, D., Kelly, W., Shannon, M., Jieming Qi, Xu, H. H., Natonio, J., Rasmus, T., Jong-Ru Guo, Wielgos, M., Garlett, J., Sorna, M. A., Meghelli, M.
Published in IEEE journal of solid-state circuits (01.08.2012)

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Journal Article Conference Proceeding

A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology

A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology

by Gangasani, G. R., Chun-Ming Hsu, Bulzacchelli, J. F., Rylov, S., Beukema, T., Freitas, D., Kelly, W., Shannon, M., Jieming Qi, Xu, H. H., Natonio, J., Rasmus, T., Jong-Ru Guo, Wielgos, M., Garlett, J., Sorna, M. A., Meghelli, M.
Published in 2011 IEEE Custom Integrated Circuits Conference (CICC) (01.09.2011)

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Conference Proceeding

High-speed polysilicon resonant-cavity photodiode with SiO2-Si Bragg reflectors

High-speed polysilicon resonant-cavity photodiode with SiO2-Si Bragg reflectors

by Bean, J.C., Jieming Qi, Schow, C.L., Li, R., Nie, H., Schaub, J., Campbell, J.C.
Published in IEEE photonics technology letters (01.06.1997)

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Journal Article

Quadrature circuit interconnect architecture with clock forwarding

Quadrature circuit interconnect architecture with clock forwarding

by Qi, Jieming, Sperling, Michael, English, Erik, Dreps, Daniel Mark
Year of Publication 07.05.2024

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Patent

QUADRATURE CIRCUIT INTERCONNECT ARCHITECTURE WITH CLOCK FORWARDING

QUADRATURE CIRCUIT INTERCONNECT ARCHITECTURE WITH CLOCK FORWARDING

by Qi, Jieming, Sperling, Michael, English, Erik, Dreps, Daniel Mark
Year of Publication 21.03.2024

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Patent

Single-lock delay locked loop with cycle counter and method therefor

Single-lock delay locked loop with cycle counter and method therefor

by Willey, Aaron, Qi, Jieming
Year of Publication 02.04.2019

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Patent

SINGLE-LOCK DELAY LOCKED LOOP WITH CYCLE COUNTER AND METHOD THEREFOR

SINGLE-LOCK DELAY LOCKED LOOP WITH CYCLE COUNTER AND METHOD THEREFOR

by Willey, Aaron, Qi, Jieming
Year of Publication 06.12.2018

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Patent

Single-lock delay locked loop with cycle counter and method therefor

Single-lock delay locked loop with cycle counter and method therefor

by Qi, Jieming, Willey, Aaron D
Year of Publication 31.03.2020

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Patent

Communication systems for power supply noise reduction

Communication systems for power supply noise reduction

by Krolak, David J, Qi, Jieming, English, Erik, Sperling, Michael, Dreps, Daniel Mark
Year of Publication 17.09.2024

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Patent

Calibrating a quadrature receive serial interface

Calibrating a quadrature receive serial interface

by Qi, Jieming, English, Erik, Sperling, Michael, Spear, Michael B, Dreps, Daniel Mark
Year of Publication 30.04.2024

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Patent

Single-lock delay locked loop with cycle counter and method therefore

Single-lock delay locked loop with cycle counter and method therefore

by Qi, Jieming, Willey, Aaron D
Year of Publication 21.08.2018

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Patent

Dynamically calibrating the offset of a receiver with a decision feedback equalizer (DFE) while performing data transport operations

Dynamically calibrating the offset of a receiver with a decision feedback equalizer (DFE) while performing data transport operations

by Chen Minhan, Qi Jieming
Year of Publication 13.09.2016

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Patent

Dual duty cycle correction loop for a serializer/deserializer (SerDes) transmitter output

Dual duty cycle correction loop for a serializer/deserializer (SerDes) transmitter output

by Lukes, Eric John, Qi, Jieming, Wiedemeier, Glen A, Dickson, Timothy O, Cox, Carrie Ellen, Dreps, Daniel Mark
Year of Publication 31.10.2023

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Patent

DUAL DUTY CYCLE CORRECTION LOOP FOR A SERIALIZER/DESERIALIZER (SERDES) TRANSMITTER OUTPUT

DUAL DUTY CYCLE CORRECTION LOOP FOR A SERIALIZER/DESERIALIZER (SERDES) TRANSMITTER OUTPUT

by Lukes, Eric John, Qi, Jieming, Wiedemeier, Glen A, Dickson, Timothy O, Cox, Carrie Ellen, Dreps, Daniel Mark
Year of Publication 24.08.2023

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Patent

Method and apparatus for use in booth-encoded multiplication

Method and apparatus for use in booth-encoded multiplication

by Qi, Jieming
Year of Publication 04.04.2006

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Patent

Structure for managing voltage swings across field effect transistors

Structure for managing voltage swings across field effect transistors

by Boerstler, David William, Qi, Jieming
Year of Publication 12.06.2012

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Patent

Method and apparatus for use in booth-encoded multiplication

Method and apparatus for use in booth-encoded multiplication

by Qi, Jieming
Year of Publication 26.06.2003

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Patent

High-speed polysilicon resonant-cavity photodiode with SiO/sub 2/-Si Bragg reflectors

High-speed polysilicon resonant-cavity photodiode with SiO/sub 2/-Si Bragg reflectors

by Bean, J.C., Jieming Qi, Schow, C.L., Li, R., Nie, H., Schaub, J., Campbell, J.C.
Published in IEEE photonics technology letters (01.06.1997)

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Journal Article

Method and system for managing voltage swings across field effect transistors

Method and system for managing voltage swings across field effect transistors

by Boerstler, David William, Qi, Jieming
Year of Publication 20.04.2010

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Patent

Structure for precision integrated phase lock loop circuit loop filter

Structure for precision integrated phase lock loop circuit loop filter

by Boerstler, David William, Qi, Jieming
Year of Publication 06.04.2010

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Patent

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