A synthesis method for MVL reversible logic [multiple value logic]
Miller, D.M., Dueck, G.W., Maslov, D.
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
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Conference Proceeding
On universality of general reversible multiple-valued logic gates
Kerntopf, P., Perkowski, M.A., Khan, M.H.A.
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
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Conference Proceeding
Ternary Galois field expansions for reversible logic and Kronecker decision diagrams for ternary GFSOP minimization [Galois field sum of products]
Khan, M.H.A., Perkowski, M.A., Khan, M.R.
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
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Conference Proceeding
Intra-chip address-presetting data-transfer scheme using four-valued encoding
Mochizuki, A., Takeuchi, T., Hanyu, T.
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
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Conference Proceeding
Spectra generation for fixed-polarity Reed-Muller transform over GF(5)
Falkowski, B.J., Lozano, C.C., Rahardja, S.
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
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Conference Proceeding
A single-electron-transistor logic gate family and its application - Part I: basic components for binary, multiple-valued and mixed-mode logic
Degawa, K., Aoki, T., Higuchi, T., Inokawa, H., Takahashi, A.
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
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Conference Proceeding
A novel multiple-valued logic design using ballistic carbon nanotube FETs
Raychowdhury, A., Roy, K.
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
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Conference Proceeding
Non-deterministic matrices
Avron, A., Lev, I.
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
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Conference Proceeding
A single-electron-transistor logic gate family and its application - Part II: design and simulation of a 7-3 parallel counter with linear summation and multiple-valued latch functions
Inokawa, H., Takahashi, Y.
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
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Conference Proceeding
Monoids whose centralizer is the least clone
Machida, H., Rosenberg, N.G.
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
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Conference Proceeding
Minimal partial hyperclones on a two-element set
Pantovic, J., Vojvodic, G.
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
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Conference Proceeding
A novel D-latch in multiple-valued semi-floating-gate recharged logic
Mirmotahari, O., Berg, Y.
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
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Conference Proceeding
Algorithms for Taylor expansion diagrams [IC design/verification applications]
Fey, G., Drechsler, R., Ciesielski, M.
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
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Conference Proceeding
Optimizing the defuzzifier timing for the fuzzy control of a servodrive
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Conference Proceeding