Test selection based on high level fault simulation for mixed-signal systems
Get full text
Conference Proceeding
Hidden Markov and independence models with patterns for sequential BIST
Brehelin, L., Gascuel, O., Caraux, G., Girard, P., Landrault, C.
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Get full text
Conference Proceeding
Testability alternatives exploration through functional testing
Ferrandi, F., Ferrara, G., Fornara, G., Fummi, F., Sciuto, D.
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Get full text
Conference Proceeding
On testing the path delay faults of a microprocessor using its instruction set
Wei-Cheng Lai, Krstic, A., Kwang-Ting Cheng
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Get full text
Conference Proceeding
Integrating logic BIST in VLSI designs with embedded memories
Chickermane, V., Richter, S., Barnhart, C.
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Get full text
Conference Proceeding
Cold delay defect screening
Chao-Wen Tseng, Mccluskey, E.J., Xiaoping Shao, Wu, D.M.
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Get full text
Conference Proceeding
Validation of PowerPC/sup TM/ custom memories using symbolic simulation
Krishnamurthy, N., Martin, A.K., Abadir, M.S., Abraham, J.A.
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Get full text
Conference Proceeding
Testing, verification, and diagnosis in the presence of unknowns
Jain, A., Boppana, V., Mukherjee, R., Jain, J., Fujita, M., Hsiao, M.
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Get full text
Conference Proceeding
SIFAR: static test compaction for synchronous sequential circuits based on single fault restoration
Xijiang Lin, Wu-Tung Cheng, Pomeranz, I., Reddy, S.M.
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Get full text
Conference Proceeding
High-level observability for effective high-level ATPG
Corno, F., Reorda, M.S., Squillero, G.
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Get full text
Conference Proceeding
Delta Iddq for testing reliability
Powell, T.J., Pair, J., St. John, M., Counce, D.
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Get full text
Conference Proceeding
Thermal testing: fault location strategies
Altet, J., Rubio, A., Schaub, E., Dialhaire, S., Claeys, W.
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Get full text
Conference Proceeding
Simulation-based test algorithm generation for random access memories
Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Get full text
Conference Proceeding
Fault escapes in duplex systems
Mitra, S., Saxena, N.R., McCluskey, E.J.
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)
Get full text
Conference Proceeding