A New Twin Flash™ Cell for 2 and 4 Bit Operation at 63nm Feature Size
Nagel, N., Boubekeur, H., Heinrichsdorff, F., Bach, L., Polei, V., Gupta, J., Pritchard, D., Riedel, S., Strassburg, M., Deppe, J., Bewersdorff-Sarlette, U., Muller, T., Verhoeven, M., Lattard, L., Markert, M., Ruttkowski, E., Mikalo, R., Willer, J., Schulze, N., Ludwig, C., v. Kamienski, E.G. Stein, Mikolajick, T., Isler, M., Kusters, K.-H., Shappir, A., Shur, Y., Lusky, E., Eitan, B., Pissors, V., Sachse, J.-U., Manger, D., Caspary, D., Parascandola, S., Olligs, D.
Published in 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) (01.04.2007)
Published in 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) (01.04.2007)
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