28nm FDSOI technology platform for high-speed low-voltage digital applications
Planes, N., Weber, O., Barral, V., Haendler, S., Noblet, D., Croain, D., Bocat, M., Sassoulas, P., Federspiel, X., Cros, A., Bajolet, A., Richard, E., Dumont, B., Perreau, P., Petit, D., Golanski, D., Fenouillet-Beranger, C., Guillot, N., Rafik, M., Huard, V., Puget, S., Montagner, X., Jaud, M., Rozeau, O., Saxod, O., Wacquant, F., Monsieur, F., Barge, D., Pinzelli, L., Mellier, M., Boeuf, F., Arnaud, F., Haond, M.
Published in 2012 Symposium on VLSI Technology (VLSIT) (01.06.2012)
Published in 2012 Symposium on VLSI Technology (VLSIT) (01.06.2012)
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Impact of a 10 nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32 nm node and below
Fenouillet-Beranger, C., Perreau, P., Denorme, S., Tosti, L., Andrieu, F., Weber, O., Monfray, S., Barnola, S., Arvet, C., Campidelli, Y., Haendler, S., Beneyton, R., Perrot, C., de Buttet, C., Gros, P., Pham-Nguyen, L., Leverd, F., Gouraud, P., Abbate, F., Baron, F., Torres, A., Laviron, C., Pinzelli, L., Vetier, J., Borowiak, C., Margain, A., Delprat, D., Boedt, F., Bourdelle, K., Nguyen, B.-Y., Faynot, O., Skotnicki, T.
Published in Solid-state electronics (01.09.2010)
Published in Solid-state electronics (01.09.2010)
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Challenges and opportunity in performance, variability and reliability in sub-45 nm CMOS technologies
ARNAUD, F, PINZELLI, L, GALLON, C, RAFIK, M, MORA, P, BOEUF, F
Published in Microelectronics and reliability (01.09.2011)
Published in Microelectronics and reliability (01.09.2011)
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Challenges in CMOS-based images
Roy, Francois, Tournier, A., Wehbe-Alause, H., Blanchet, F., Boulenc, P., Leverd, F., Favennec, L., Perrot, C., Pinzelli, L., Gatefait, M., Cherault, N., Jeanjean, D., Carrere, J. P., Augier, C., Ricq, S., Herault, D., Hulot, S.
Published in Physica status solidi. C (01.01.2014)
Published in Physica status solidi. C (01.01.2014)
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Journal Article
Efficient multi-VT FDSOI technology with UTBOX for low power circuit design
Fenouillet-Beranger, C, Thomas, O, Perreau, P, Noel, J.-P, Bajolet, A, Haendler, S, Tosti, L, Barnola, S, Beneyton, R, Perrot, C, de Buttet, C, Abbate, F, Baron, F, Pernet, B, Campidelli, Y, Pinzelli, L, Gouraud, P, Cassé, M, Borowiak, C, Weber, O, Andrieu, F, Denorme, S, Boeuf, F, Faynot, O, Skotnicki, T, Bourdelle, K K, Nguyen, B Y, Boedt, F
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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Conference Proceeding
Multigate MOSFET in a Bulk Technology by Integrating Polysilicon-Filled Trenches
Ramadout, B., Guo-Neng Lu, Carrere, J.-P., Pinzelli, L., Perrot, C., Rivoire, M., Nemouchi, F.
Published in IEEE electron device letters (01.12.2009)
Published in IEEE electron device letters (01.12.2009)
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Journal Article
Impact of a 10nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32nm node and below
Fenouillet-Beranger, C., Perreau, P., Denorme, S., Tosti, L., Andrieu, F., Weber, O., Monfray, S., Barnola, S., Arvet, C., Campidelli, Y., Haendler, S., Beneyton, R., Perrot, C., de Buttet, C., Gros, P., Pham-Nguyen, L., Leverd, F., Gouraud, P., Abbate, F., Baron, F., Torres, A., Laviron, C., Pinzelli, L., Vetier, J., Borowiak, C., Margain, A., Delprat, D., Boedt, F., Bourdelle, K., Nguyen, B.-Y., Faynot, O., Skotnicki, T.
Published in Solid-state electronics (01.09.2010)
Published in Solid-state electronics (01.09.2010)
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Cu surface treatment influence on Si adsorption properties of CuSiN self-aligned barriers for sub-65 nm technology node
Chhun, S., Gosset, L.G., Michelon, J., Girault, V., Vitiello, J., Hopstaken, M., Courtas, S., Debauche, C., Bancken, P.H.L., Gaillard, N., Bryce, G., Juhel, M., Pinzelli, L., Guillan, J., Gras, R., Van Schravendijk, B., Dupuy, J.-C., Torres, J.
Published in Microelectronic engineering (01.11.2006)
Published in Microelectronic engineering (01.11.2006)
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High-K dielectric deposition in 3D architectures: The case of Ta2O5 deposited with metal-organic precursor TBTDET
PINZELLI, L, GROS-JEAN, M, BRECHET, Y, VOLPI, F, BAJOLET, A, GIRAUDIN, J.-C
Published in Microelectronics and reliability (01.04.2007)
Published in Microelectronics and reliability (01.04.2007)
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A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications
Boeuf, F., Cremer, S., Vulliet, N., Pinguet, T., Mekis, A., Masini, G., Verslegers, L., Sun, P., Ayazi, A., Hon, N-K, Sahni, S., Chi, Y., Orlando, B., Ristoiu, D., Farcy, A., Leverd, F., Broussous, L., Pelissier-Tanon, D., Richard, C., Pinzelli, L., Beneyton, R., Gourhant, O., Gourvest, E., Le-Friec, Y., Monnier, D., Brun, P., Guillermet, M., Benoit, D., Haxaire, K., Manouvrier, J. R., Jan, S., Petiton, H., Carpentier, J. F., Quemerais, T., Durand, C., Gloria, D., Fourel, M., Battegay, F., Sanchez, Y., Batail, E., Baron, F., Delpech, P., Salager, L., De Dobbelaere, P., Sautreuil, B.
Published in 2013 IEEE International Electron Devices Meeting (01.12.2013)
Published in 2013 IEEE International Electron Devices Meeting (01.12.2013)
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Conference Proceeding
Journal Article
Challenges and opportunity in performance, variability and reliability in sub-45nm CMOS technologies
Arnaud, F., Pinzelli, L., Gallon, C., Rafik, M., Mora, P., Boeuf, F.
Published in Microelectronics and reliability (01.09.2011)
Published in Microelectronics and reliability (01.09.2011)
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Journal Article
A solution for an ideal planar multi-gates process for ultimate CMOS?
Monfray, S, Huguenin, J, Martin, M, Samson, M, Borowiak, C, Arvet, C, Dalemcourt, J, Perreau, P, Barnola, S, Bidal, G, Denorme, S, Campidelli, Y, Benotmane, K, Leverd, F, Gouraud, P, Le-Gratiet, B, De-Buttet, C, Pinzelli, L, Beneyton, R, Morel, T, Wacquez, R, Bustos, J, Icard, B, Pain, L, Barraud, S, Ernst, T, Boeuf, F, Faynot, O, Skotnicki, T
Published in 2010 International Electron Devices Meeting (01.12.2010)
Published in 2010 International Electron Devices Meeting (01.12.2010)
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Conference Proceeding
Dopant diffusion and activation induced by sub-melt laser anneal within the co-implanted p+ polycrystalline silicon gate used in CMOS technologies
Colin, A., Morin, P., Beneyton, R., Pinzelli, Luc, Mathiot, D., Fogarassy, E.
Published in Thin solid films (2010)
Published in Thin solid films (2010)
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Conference Proceeding
UTBOX and ground plane combined with Al2O3 inserted in TiN gate for VT modulation in fully-depleted SOI CMOS transistors
Fenouillet-Beranger, C, Perreau, P, Casse, M, Garros, X, Leroux, C, Martin, F, Gassilloud, R, Bajolet, A, Tosti, L, Barnola, S, Andrieu, F, Weber, O, Beneyton, R, Perrot, C, de Buttet, C, Abbate, F, Pernet, B, Campidelli, Y, Pinzelli, L, Gouraud, P, Huguenin, J L, Borowiak, C, Peru, S, Clement, L, Pantel, R, Bourdelle, K K, Nguyen, B Y, Boedt, F, Denorme, S, Faynot, O, Skotnicki, T, Boeuf, F
Published in Proceedings of 2011 International Symposium on VLSI Technology, Systems and Applications (01.04.2011)
Published in Proceedings of 2011 International Symposium on VLSI Technology, Systems and Applications (01.04.2011)
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Conference Proceeding
Parasitic bipolar impact in 32ANBnm undoped channel Ultra-Thin BOX (UTBOX) and biased Ground Plane FDSOI high-k/metal gate technology
Fenouillet-Beranger, C, Perreau, P, Boulenc, P, Tosti, L, Barnola, S, Andrieu, F, Weber, O, Beneyton, R, Perrot, C, de Buttet, C, Abbate, F, Campidelli, Y, Pinzelli, L, Gouraud, P, Margain, A, Peru, S, Bourdelle, K K, Nguyen, B Y, Boedt, F, Poiroux, T, Faynot, O, Skotnicki, T, Boeuf, F
Published in Solid-state electronics (01.08.2012)
Published in Solid-state electronics (01.08.2012)
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Journal Article
Parasitic bipolar impact in 32nm undoped channel Ultra-Thin BOX (UTBOX) and biased Ground Plane FDSOI high-k/metal gate technology
Fenouillet-Beranger, C., Perreau, P., Boulenc, P., Tosti, L., Barnola, S., Andrieu, F., Weber, O., Beneyton, R., Perrot, C., de Buttet, C., Abbate, F., Campidelli, Y., Pinzelli, L., Gouraud, P., Margain, A., Peru, S., Bourdelle, K.K., Nguyen, B.Y., Boedt, F., Poiroux, T., Faynot, O., Skotnicki, T., Boeuf, F.
Published in Solid-state electronics (01.08.2012)
Published in Solid-state electronics (01.08.2012)
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Journal Article
Parasitic bipolar impact in 32 nm undoped channel Ultra-Thin BOX (UTBOX) and biased Ground Plane FDSOI high-k/metal gate technology: Selected Papers from the ESSDERC 2011 Conference
FENOUILLET-BERANGER, C, PERREAU, P, ABBATE, F, CAMPIDELLI, Y, PINZELLI, L, GOURAUD, P, MARGAIN, A, PERU, S, BOURDELLE, K. K, NGUYEN, B. Y, BOEDT, F, POIROUX, T, BOULENC, P, FAYNOT, O, SKOTNICKI, T, BOEUF, F, TOSTI, L, BARNOLA, S, ANDRIEU, F, WEBER, O, BENEYTON, R, PERROT, C, DE BUTTER, C
Published in Solid-state electronics (2012)
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Published in Solid-state electronics (2012)
Journal Article
Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below
Fenouillet-Beranger, C., Perreau, P., Denorme, S., Tosti, L., Andrieu, F., Weber, O., Barnola, S., Arvet, C., Campidelli, Y., Haendler, S., Beneyton, R., Perrot, C., de Buttet, C., Gros, P., Pham-Nguyen, L., Leverd, F., Gouraud, P., Abbate, F., Baron, F., Torres, A., Laviron, C., Pinzelli, L., Vetier, J., Borowiak, C., Margain, A., Delprat, D., Boedt, F., Bourdelle, K., Nguyen, B.-Y., Faynot, O., Skotnicki, T.
Published in 2009 Proceedings of the European Solid State Device Research Conference (01.09.2009)
Published in 2009 Proceedings of the European Solid State Device Research Conference (01.09.2009)
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Conference Proceeding
Parasitic bipolar impact in 32nm undoped channel Ultra-Thin BOX (UTBOX) and biased ground plane FDSOI high-k/metal gate technology
Fenouillet-Beranger, C., Perreau, P., Boulenc, P., Tosti, L., Barnola, S., Andrieu, F., Weber, O., Beneyton, R., Perrot, C., de Buttet, C., Abbate, F., Campidelli, Y., Pinzelli, L., Gouraud, P., Margain, A., Peru, S., Bourdelle, K. K., Nguyen, B. Y., Boedt, F., Poiroux, T., Faynot, O., Skotnicki, T., Boeuf, F.
Published in 2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC) (01.09.2011)
Published in 2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC) (01.09.2011)
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