The circuit and physical design of the POWER4 microprocessor
Warnock, J. D., Keaty, J. M., Petrovick, J., Clabes, J. G., Kircher, C. J., Krauter, B. L., Restle, P. J., Zoric, B. A., Anderson, C. J.
Published in IBM journal of research and development (01.01.2002)
Published in IBM journal of research and development (01.01.2002)
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Journal Article
Physical design of a fourth-generation POWER GHz microprocessor
Anderson, C.J., Petrovick, J., Keaty, J.M., Warnock, J., Nussbaum, G., Tendier, J.M., Carter, C., Chu, S., Clabes, J., DiLullo, J., Dudley, P., Harvey, P., Krauter, B., LeBlanc, J., Pong-Fei Lu, McCredie, B., Plum, G., Restle, P.J., Runyon, S., Scheuermann, M., Schmidt, S., Wagoner, J., Weiss, R., Weitzel, S., Zoric, B.
Published in 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177) (2001)
Published in 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177) (2001)
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Conference Proceeding
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A clock distribution network for microprocessors
Restle, P.J., McNamara, T.G., Webber, D.A., Camporese, P.J., Eng, K.F., Jenkins, K.A., Allen, D.H., Rohn, M.J., Quaranta, M.P., Boerstler, D.W., Alpert, C.J., Carter, C.A., Bailey, R.N., Petrovick, J.G., Krauter, B.L., McCredie, B.D.
Published in IEEE journal of solid-state circuits (01.05.2001)
Published in IEEE journal of solid-state circuits (01.05.2001)
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Journal Article
Mass-Transport Resistances of Acid and Alkaline Ionomer Layers: A Microelectrode Study Part 1 - Microelectrode Development
Petrovick, John G., Kushner, Douglas I., Tesfaye, Meron, Danilovic, Nemanja, Radke, Clayton J., Weber, Adam Z.
Published in ECS transactions (03.07.2019)
Published in ECS transactions (03.07.2019)
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Journal Article
Low-cost testing of high-density logic components
Bassett, R.W., Butkus, B.J., Dingle, S.R., Faucher, M.R., Gillis, P.S., Panner, J.H., Petrovick, J.G., Wheater, D.L.
Published in IEEE design & test of computers (01.04.1990)
Published in IEEE design & test of computers (01.04.1990)
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Journal Article
Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor
Pham, D., Anderson, H.W., Behnen, E., Bolliger, M., Gupta, S., Hofstee, P., Harvey, P., Johns, C., Kahle, J., Kameyama, A., Keaty, J., Le, B., Sang Lee, Tuyen Nguyen, Petrovick, J., Mydung Pham Pille, J., Posluszny, S., Riley, M., Verock, J., Warnock, J., Weitzel, S., Wendel, D.
Published in Asia and South Pacific Conference on Design Automation, 2006 (2006)
Published in Asia and South Pacific Conference on Design Automation, 2006 (2006)
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Conference Proceeding
Fault detection for a distributed signal line
OREFICE ROBERT S, PETROVICK, JR. JOHN G, KOSONOCKY STEPHEN V, PRIORE DONALD A
Year of Publication 29.03.2016
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Year of Publication 29.03.2016
Patent
FAULT DETECTION FOR A DISTRIBUTED SIGNAL LINE
OREFICE ROBERT S, PETROVICK, JR. JOHN G, KOSONOCKY STEPHEN V, PRIORE DONALD A
Year of Publication 20.11.2014
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Year of Publication 20.11.2014
Patent
A 300 K-circuit ASIC logic family
Petrovick, J., Taylor, R., Bertolet, A., Chu, A., Harroun, T., Keyser, F., LaMarche, C., Pastel, L., Richardson, G., Worth, B.
Published in 1990 37th IEEE International Conference on Solid-State Circuits (1990)
Published in 1990 37th IEEE International Conference on Solid-State Circuits (1990)
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Conference Proceeding
A clock methodology for high-performance microprocessors
Carrig, K.M., Chu, A.M., Ferraiolo, F.D., Perovick, J.G., Scott, P.A., Weiss, R.J.
Published in Proceedings of CICC 97 - Custom Integrated Circuits Conference (1997)
Published in Proceedings of CICC 97 - Custom Integrated Circuits Conference (1997)
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Conference Proceeding
Branch isolation circuit for cascode voltage switch logic
BERTOLET; ALLAN R, PETROVICK, JR.; JOHN G, GRIFFIN; WILLIAM R, CHU; ALBERT M, WISSEL; LARRY
Year of Publication 14.02.1995
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Year of Publication 14.02.1995
Patent
Clock methodology for high-performance microprocessors
Carrig, Keith M, Chu, Albert M, Ferraiolo, Frank D, Petrovick, John G, Scott, P Andrew, Weiss, Richard J
Published in Journal of VLSI signal processing (01.06.1997)
Published in Journal of VLSI signal processing (01.06.1997)
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Journal Article
Macro performance test
PETROVICK, JR.; JOHN G, GRIFFIN; WILLIAM R, MURPHY; SUSAN A, VARNER; JAMES R, BASSETT; ROBERT W, WHITTAKER; DENNIS R
Year of Publication 31.10.1989
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Year of Publication 31.10.1989
Patent
Embedded array access time test
BASSETT, ROBERT WALTER, GRIFFIN, WILLIAM R, MURPHY, SUSAN ANN, PETROVICK, JOHN GEORGE, JR, VARNER, JAMES ROBERT, WHITTAKER, DENNIS ROBERT
Year of Publication 06.12.1995
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Year of Publication 06.12.1995
Patent
EMBEDDED ARRAY ACCESS TIME TEST
BASSETT, ROBERT WALTER, GRIFFIN, WILLIAM R, MURRAY, SUSAN ANN, PETROVICK, JOHN GEORGE, JR, VARNER, JAMES ROBERT, WHITTAKER, DENNIS ROBERT
Year of Publication 03.07.1991
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Year of Publication 03.07.1991
Patent
Embedded array access time test
BASSETT, ROBERT WALTER, GRIFFIN, WILLIAM R, MURRAY, SUSAN ANN, PETROVICK, JOHN GEORGE, JR, VARNER, JAMES ROBERT, WHITTAKER, DENNIS ROBERT
Year of Publication 18.10.1989
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Year of Publication 18.10.1989
Patent
Zugriffszeitprüfung eingegrabener Anordnungen
VARNER, JAMES ROBERT, ESSEX JUNCTION, VT 05452, US, MURPHY, SUSAN ANN, SOUTH BURLINGTON, VT. 05403, US, BASSETT, ROBERT WALTER, ESSEX JUNCTION, VT. 05452, US, GRIFFIN, WILLIAM R., SHELBURNE, VT. 05482, US, PETROVICK, JOHN GEORGE, JR., COLCHESTER, VT. 05446, US, WHITTAKER, DENNIS ROBERT, FAIRFAX, VIRGINIA 22032, US
Year of Publication 20.06.1996
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Year of Publication 20.06.1996
Patent