A Formal Verification Method of Scheduling in High-level Synthesis
Karfa, C, Mandal, C, Sarkar, D, Pentakota, S R., Reade, Chris
Published in 7th International Symposium on Quality Electronic Design (ISQED'06) (01.01.2006)
Published in 7th International Symposium on Quality Electronic Design (ISQED'06) (01.01.2006)
Get full text
Conference Proceeding
Verification of scheduling in high-level synthesis
Karfa, C., Mandal, C., Sarkar, D., Pentakota, S.R., Reade, C.
Published in IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06) (01.06.2006)
Published in IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06) (01.06.2006)
Get full text
Conference Proceeding