Interconnect-Centric High Level Synthesis for Enhanced Layouts with Reduced Wire Length
Parakh, P., Mullassery, D., Chandrashekar, A., Koc, H., Dal, D., Mansouri, N.
Published in 2006 49th IEEE International Midwest Symposium on Circuits and Systems (01.08.2006)
Published in 2006 49th IEEE International Midwest Symposium on Circuits and Systems (01.08.2006)
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Conference Proceeding
An FPGA-based MOS circuit simulator
Deepaksubramanyan, B.S., Parakh, P., Zhenhua Chen, Diab, H., Marcy, D., Schlereth, F.H.
Published in 48th Midwest Symposium on Circuits and Systems, 2005 (2005)
Published in 48th Midwest Symposium on Circuits and Systems, 2005 (2005)
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Conference Proceeding
Propagation simulation buffer for clock domain crossing
Grenat Aaron J, Parakh Priyank, Kidd Joseph, Tresidder Michael J, Kommrusch Steven J, Osborn Michael J
Year of Publication 11.04.2017
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Year of Publication 11.04.2017
Patent
PROPAGATION SIMULATION BUFFER
OSBORN MICHAEL J, TRESIDDER MICHAEL J, KOMMRUSCH STEVEN J, PARAKH PRIYANK, GRENAT AARON J, KIDD JOSEPH
Year of Publication 06.03.2014
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Year of Publication 06.03.2014
Patent
Clock domain crossing buffer
OSBORN MICHAEL J, TRESIDDER MICHAEL J, KOMMRUSCH STEVEN J, PARAKH PRIYANK, GRENAT AARON J, KIDD JOSEPH
Year of Publication 12.11.2013
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Year of Publication 12.11.2013
Patent
CLOCK DOMAIN CROSSING BUFFER
OSBORN MICHAEL J, TRESIDDER MICHAEL J, KOMMRUSCH STEVEN J, PARAKH PRIYANK, GRENAT AARON J, KIDD JOSEPH
Year of Publication 03.05.2012
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Year of Publication 03.05.2012
Patent