Search Results - "Pappu, Lakshminarayana" :: K.UTB vyhledávací portál

Loading…

A/V LOW LATENCY COMMUNICATION PATH FOR AUDIO/VISUALA/V APPLICATIONS

by ANSARI NAUSHEEN, HECK HOWARD, PAPPU LAKSHMINARAYANA, SRIVASTAVA AMIT KUMAR
Year of Publication 17.05.2023

Get full text

Patent

Loading…

SOC SOC ARCHITECTURE TO REDUCE MEMORY BANDWIDTH BOTTLENECKS AND FACILITATE POWER MANAGEMENT

by MENDON ASHWIN A, ANSARI NAUSHEEN, PAPPU LAKSHMINARAYANA, HECK HOWARD L, HARRIMAN DAVID J
Year of Publication 30.06.2023

Get full text

Patent

Loading…

Touch host controller

by Pappu, Lakshminarayana
Year of Publication 23.06.2020

Get full text

Patent

Loading…

Display controller testing through high speed communications switch

by Pappu, Lakshminarayana
Year of Publication 10.09.2019

Get full text

Patent

Loading…

Protocol aware testing engine for high speed link integrity testing

by Pappu, Lakshminarayana
Year of Publication 09.07.2019

Get full text

Patent

Loading…

TOUCH HOST CONTROLLER

by Pappu, Lakshminarayana
Year of Publication 04.04.2019

Get full text

Patent

Loading…

DISPLAY CONTROLLER TESTING THROUGH HIGH SPEED COMMUNICATIONS SWITCH

by Pappu, Lakshminarayana
Year of Publication 20.09.2018

Get full text

Patent

Loading…

MECHANISM TO PROVIDE BACK-TO-BACK TESTING OF MEMORY CONTROLLER OPERATION

by Pappu, Lakshminarayana
Year of Publication 30.08.2018

Get full text

Patent

Loading…

Systems, methods, and apparatuses for implementing testing of a far memory subsystem within two-level memory (2LM) stacked die subsystems

by Pappu, Lakshminarayana
Year of Publication 21.08.2018

Get full text

Patent

Loading…

Methods and apparatus to reduce display connection latency

by Pappu, Lakshminarayana, Witter, Todd, Ansari, Nausheen
Year of Publication 15.10.2024

Get full text

Patent

Loading…

SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING TESTING OF A FAR MEMORY SUBSYSTEM WITHIN TWO-LEVEL MEMORY (2LM) STACKED DIE SUBSYSTEMS

by PAPPU LAKSHMINARAYANA
Year of Publication 05.04.2018

Get full text

Patent

Loading…

Protocol Aware Testing Engine for High Speed Link Integrity Testing

by PAPPU Lakshminarayana
Year of Publication 05.04.2018

Get full text

Patent

Loading…

INFRASTRUCTURE FOR PLATFORM IMMERSIVE EXPERIENCE

by Shah, Ankur N, Pappu, Lakshminarayana, Ramadoss, Murali
Year of Publication 13.04.2023

Get full text

Patent

Loading…

System-on-a-Chip (SoC) Architecture for Low Power State Communication

by Kanumuri, Naveen, Koker, Altug, Pappu, Lakshminarayana
Year of Publication 13.04.2023

Get full text

Patent

Loading…

SYSTEM, METHOD, APPARATUS AND ARCHITECTURE FOR DYNAMICALLY CONFIGURING DEVICE FABRICS

by NAGARAJAN, Ramadass, PAPPU, Lakshminarayana, NATU, Mahesh S, HARRIMAN, David J
Year of Publication 30.10.2024

Get full text

Patent

Loading…

METHODS AND APPARATUS TO REDUCE DISPLAY CONNECTION LATENCY

by Pappu, Lakshminarayana, Witter, Todd, Ansari, Nausheen
Year of Publication 15.09.2022

Get full text

Patent

Loading…

Phase lock loop bypass for board-level testing of systems

by Pappu, Lakshminarayana, Schnarch, Baruch
Year of Publication 28.05.2019

Get full text

Patent

Loading…

Device, system and method for on-chip testing of protocol stack circuitry

by Lasker, Yonah, Pappu, Lakshminarayana
Year of Publication 22.01.2019

Get full text

Patent

Loading…

DEVICE, SYSTEM AND METHOD FOR ON-CHIP TESTING OF PROTOCOL STACK CIRCUITRY

by PAPPU, Lakshminarayana, LASKER, Yonah
Year of Publication 04.10.2018

Get full text

Patent

Loading…

PHASE LOCK LOOP BYPASS FOR BOARD-LEVEL TESTING OF SYSTEMS

by PAPPU, Lakshminarayana, SCHNARCH, Baruch
Year of Publication 27.09.2018

Get full text

Patent

Refine Results

Format

Subject Area

Topic

Language

Year of Publication

Database