Search Results - "Pachamuthu Jayavel" :: K.UTB vyhledávací portál

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Program disturb improvements in multi-tier memory devices including improved non-data conductive gate implementation

by Zhao, Dengtao, Pachamuthu, Jayavel
Year of Publication 31.08.2021

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Patent

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Generation of Electricity by Thermophotovoltaic Cells using a pseudo Blackbody Surface

by Hanamura, Katsunori, Taniguchi, Yuji, Jayavel, Pachamuthu, Srinivasan, Elaiyaraju, Fukai, Hirofumi, Yamada, Akira
Published in Netsu Bussei (2014)

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Journal Article

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Three-dimensional memory device having enhanced contact between polycrystalline channel and epitaxial pedestal structure and method of making the same

by Nishikawa, Masatoshi, Pachamuthu, Jayavel
Year of Publication 27.04.2021

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Patent

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Three-dimensional memory device having enhanced contact between polycrystalline channel and epitaxial pedestal structure and method of making the same

by Nishikawa, Masatoshi, Pachamuthu, Jayavel
Year of Publication 27.04.2021

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Patent

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THREE-DIMENSIONAL MEMORY DEVICE HAVING ENHANCED CONTACT BETWEEN POLYCRYSTALLINE CHANNEL AND EPITAXIAL PEDESTAL STRUCTURE AND METHOD OF MAKING THE SAME

by NISHIKAWA, Masatoshi, PACHAMUTHU, Jayavel
Year of Publication 04.02.2021

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Patent

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THREE-DIMENSIONAL MEMORY DEVICE HAVING ENHANCED CONTACT BETWEEN POLYCRYSTALLINE CHANNEL AND EPITAXIAL PEDESTAL STRUCTURE AND METHOD OF MAKING THE SAME

by NISHIKAWA, Masatoshi, PACHAMUTHU, Jayavel
Year of Publication 04.02.2021

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Patent

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HIGH DENSITY SEMICONDUCTOR DEVICE INCLUDING INTEGRATED CONTROLLER, LOGIC CIRCUIT AND MEMORY DIES

by Sivaram, Srinivasan, Pachamuthu, Jayavel, Higashitani, Masaaki
Year of Publication 21.03.2024

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Patent

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Controlled string erase for nonvolatile memory

by Pachamuthu, Jayavel, Desai, Amul
Year of Publication 08.12.2020

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Patent

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TECHNIQUES FOR DETERMINING LAST PROGRAMMED WORDLINE

by PACHAMUTHU, JAYAVEL, PERIYANNAN, KIRUBAKARAN, LINNEN, DANIEL J
Year of Publication 14.12.2023

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Patent

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CLAMPED SEMICONDUCTOR WAFERS AND SEMICONDUCTOR DEVICES

by PERIYANNAN, Kirubakaran, LINNEN, Daniel, PACHAMUTHU, Jayavel
Year of Publication 19.10.2023

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Patent

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CLAMPED SEMICONDUCTOR WAFERS AND SEMICONDUCTOR DEVICES

by Pachamuthu, Jayavel, Linnen, Daniel, Periyannan, Kirubakaran
Year of Publication 12.10.2023

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Patent

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THREE DIMENSIONAL NAND DEVICE HAVING REDUCED WAFER BOWING AND METHOD OF MAKING THEREOF

by BAENNINGER, Matthias, ALSMEIER, Johann, PACHAMUTHU, Jayavel
Year of Publication 20.09.2023

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Patent

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System and method for warpage detection in a CMOS bonded array

by Pachamuthu, Jayavel, Linnen, Daniel, Periyannan, Kirubakaran
Year of Publication 20.06.2023

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Patent

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NON-VOLATILE MEMORY WITH EFFICIENT TESTING

by Lee, Dana, Pachamuthu, Jayavel, Yuan, Jiahui
Year of Publication 23.02.2023

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Patent

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Memory controller for resolving string to string shorts

by Paudel, Rajan, Pachamuthu, Jayavel, Bharadwaj, Deepak
Year of Publication 07.02.2023

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Patent

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System and Method for Die Crack Detection in Wafer-to-Wafer Bonding

by Skala, Stephen, Pachamuthu, Jayavel, Linnen, Daniel J, Periyannan, Kirubakaran
Year of Publication 25.07.2024

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Patent

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MEMORY CONTROLLER FOR RESOLVING STRING TO STRING SHORTS

by Paudel, Rajan, Pachamuthu, Jayavel, Bharadwaj, Deepak
Year of Publication 10.11.2022

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Patent

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Semiconductor device including coupled bond pads having differing numbers of pad legs

by Pachamuthu, Jayavel, Linnen, Daniel, Periyannan, Kirubakaran
Year of Publication 04.10.2022

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Patent

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Straight wirebonding of silicon dies

by Pachamuthu, Jayavel, Linnen, Daniel, Periyannan, Kirubakaran
Year of Publication 27.09.2022

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Patent

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System and method for die crack detection in a CMOS bonded array

by Pachamuthu, Jayavel, Linnen, Daniel, Periyannan, Kirubakaran
Year of Publication 20.09.2022

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Patent

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