A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET
Poon, Chi Fung, Zhang, Wenfeng, Cho, Junho, Ma, Shaojun, Wang, Yipeng, Cao, Ying, Laraba, Asma, Ho, Eugene, Lin, Winson, Wu, Daniel Zhaoyin, Tan, Kee Hian, Upadhyaya, Parag, Frans, Yohan
Published in IEEE journal of solid-state circuits (01.04.2022)
Published in IEEE journal of solid-state circuits (01.04.2022)
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Journal Article
A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET
Upadhyaya, Parag, Poon, Chi Fung, Lim, Siok Wei, Cho, Junho, Roldan, Arianne, Zhang, Wenfeng, Namkoong, Jin, Pham, Toan, Xu, Bruce, Lin, Winson, Zhang, Hongtao, Narang, Nakul, Tan, Kee Hian, Zhang, Geoff, Frans, Yohan, Chang, Ken
Published in IEEE journal of solid-state circuits (01.01.2019)
Published in IEEE journal of solid-state circuits (01.01.2019)
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Journal Article
A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET
Upadhyaya, Parag, Chi Fung Poon, Siok Wei Lim, Junho Cho, Roldan, Arianne, Wenfeng Zhang, Jin Namkoong, Toan Pham, Xu, Bruce, Lin, Winson, Hongtao Zhang, Narang, Nakul, Kee Hian Tan, Zhang, Geoff, Frans, Yohan, Chang, Ken
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01.02.2018)
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01.02.2018)
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Conference Proceeding
A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET
Hudner, James, Carey, Declan, Casey, Ronan, Hearne, Kay, de Abreu Farias Neto, Pedro Wilson, Chlis, Ilias, Erett, Marc, Chi Fung Poon, Laraba, Asma, Hongtao Zhang, Chaitanya Ambatipudi, Sai Lalith, Mahashin, David, Upadhyaya, Parag, Frans, Yohan, Chang, Ken
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
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Conference Proceeding
DIGITAL SIGNAL PROCESSING BLOCK WITH PREADDER STAGE
POON CHI FUNG, SIMKINS JAMES M, VADI VASISHT M, RAB MUHAMMAD A, THENDEAN JOHN M, CHING ALVIN Y, WENDLING XAVIER
Year of Publication 01.09.2011
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Year of Publication 01.09.2011
Patent
A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS
Savoj, J., Hsieh, K., Upadhyaya, P., Fu-Tai An, Bekele, A., Chen, S., Xuewen Jiang, Kang Wei Lai, Chi Fung Poon, Sewani, A., Turker, D., Venna, K., Wu, D., Xu, B., Alon, E., Ken Chang
Published in 2012 Symposium on VLSI Circuits (VLSIC) (01.06.2012)
Published in 2012 Symposium on VLSI Circuits (VLSIC) (01.06.2012)
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Conference Proceeding