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Execution Array Memory Array Processor (XarMa)

Execution Array Memory Array Processor (XarMa)

by Pechanek, Gerald G.
Published in 2020 SoutheastCon (28.03.2020)

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Conference Proceeding

A neuro-emulator with embedded capabilities for generalized learning

A neuro-emulator with embedded capabilities for generalized learning

by Aikens II, Valentine C., Delgado-Frias, José G., Pechanek, Gerald G., Vassiliadis, Stamatis
Published in Journal of systems architecture (01.07.1999)

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Journal Article

PARALLEL PROCESSING SYSTEM AND METHOD USING SURROGATE INSTRUCTIONS

PARALLEL PROCESSING SYSTEM AND METHOD USING SURROGATE INSTRUCTIONS

by CLAIR, JOHN GLOSSNER, PECHANEK, GERALD G, LARSEN, LARRY D, STAMATI, VASSILIADIS
Year of Publication 01.06.1999

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Patent

An introduction to an array memory processor for application specific acceleration

An introduction to an array memory processor for application specific acceleration

by Pechanek, Gerald G., Pitsianis, Nikos
Published in 2017 IEEE High Performance Extreme Computing Conference (HPEC) (01.09.2017)

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Conference Proceeding

Spin-L: Sequential pipelined neuroemulator with learning capabilites

Spin-L: Sequential pipelined neuroemulator with learning capabilites

by Barber, Steven M, Delgado-Frias, Jose G, Vassiliadis, Stamatis, Pechanek, Gerald G
Published in International Joint Conference on Neural Networks, Nagoya, 1993 (01.01.1993)

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Journal Article

Machine and bit precision influence on the Hopfield-Tank model for the TSP

Machine and bit precision influence on the Hopfield-Tank model for the TSP

by Wei Lin, Delgado-Frias, J.G., Vassiliadis, S., Pechanek, G.G.
Published in International Joint Conference on Neural Networks, Nagoya, 1993 (1993)

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Conference Proceeding Journal Article

Methods and apparatus for storing expanded width instructions in a VLIW memory for deferred execution

Methods and apparatus for storing expanded width instructions in a VLIW memory for deferred execution

by VASSILIADIS STAMATIS, PECHANEK GERALD G
Year of Publication 28.04.2015

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Patent

Methods and apparatus for address translation functions

Methods and apparatus for address translation functions

by Pechanek Gerald G, Barry Edwin F
Year of Publication 26.07.2016

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Patent

Methods and Apparatus for Storing Expanded Width Instructions in a VLIW Memory for Deferred Execution

Methods and Apparatus for Storing Expanded Width Instructions in a VLIW Memory for Deferred Execution

by VASSILIADIS STAMATIS, PECHANEK GERALD G
Year of Publication 19.06.2014

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Patent

Methods and apparatus for dynamically merging an array controller with an array processing element

Methods and apparatus for dynamically merging an array controller with an array processing element

by PECHANEK, GERALD G, REVILLA, JUAN GUILLERMO
Year of Publication 06.03.2013

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Patent

Methods and Apparatus for Meta-Architecture Defined Programmable Instruction Fetch Functions Supporting Assembled Variable Length Instruction Processors

Methods and Apparatus for Meta-Architecture Defined Programmable Instruction Fetch Functions Supporting Assembled Variable Length Instruction Processors

by PECHANEK GERALD G
Year of Publication 02.08.2007

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Patent

METHODS AND APPARATUS FOR EFFICIENTLY SHARING MEMORY AND PROCESSING IN A MULTI-PROCESSOR

METHODS AND APPARATUS FOR EFFICIENTLY SHARING MEMORY AND PROCESSING IN A MULTI-PROCESSOR

by PECHANEK GERALD G
Year of Publication 28.09.2006

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Patent

METHODS AND APPARATUS FOR DYNAMICALLY MERGING AN ARRAY CONTROLLER WITH AN ARRAY PROCESSING ELEMENT

METHODS AND APPARATUS FOR DYNAMICALLY MERGING AN ARRAY CONTROLLER WITH AN ARRAY PROCESSING ELEMENT

by REVILLA, JUAN, G, PECHANEK, GERALD, G
Year of Publication 16.11.2011

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Patent

Methods and apparatus for dynamically merging an array controller with an array processing element

Methods and apparatus for dynamically merging an array controller with an array processing element

by PECHANEK, GERALD G, REVILLA, JUAN GUILLERMO
Year of Publication 06.07.2011

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Patent

Methods and apparatus for dynamically merging an array controller with an array processing element

Methods and apparatus for dynamically merging an array controller with an array processing element

by PECHANEK, GERALD G, REVILLA, JUAN GUILLERMO
Year of Publication 22.06.2011

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Patent

Manifold Array Processor

Manifold Array Processor

by KURAK, JR. CHARLES W, PECHANEK GERALD G
Year of Publication 17.01.2013

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Patent

PROCESSOR DEVICE, METHOD OF OPERATING DUAL PROCESSOR, AND OPERATION METHOD FOR ARRAY PROCESSOR

PROCESSOR DEVICE, METHOD OF OPERATING DUAL PROCESSOR, AND OPERATION METHOD FOR ARRAY PROCESSOR

by REVILLA JUAN G, PECHANEK GERALD G
Year of Publication 14.01.2010

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Patent

Efficient Complex Multiplication and Fast Fourier Transform (FFT) Implementation on the ManArray Architecture

Efficient Complex Multiplication and Fast Fourier Transform (FFT) Implementation on the ManArray Architecture

by PITSIANIS NIKOS P, RODRIGUEZ RICARDO E, PECHANEK GERALD G
Year of Publication 15.09.2011

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Patent

METHODS AND APPARATUS FOR DYNAMICALLY MERGING AN ARRAY CONTROLLER WITH AN ARRAY PROCESSING ELEMENT

METHODS AND APPARATUS FOR DYNAMICALLY MERGING AN ARRAY CONTROLLER WITH AN ARRAY PROCESSING ELEMENT

by REVILLA, JUAN, G, PECHANEK, GERALD, G
Year of Publication 19.11.2008

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Patent

Manifold Array Processor

Manifold Array Processor

by PECHANEK GERALD G, KURAK CHARLES W.JR
Year of Publication 28.02.2008

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Patent

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