24.2 A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue
Fujiwara, Hidehiro, Lin, Chih-Yu, Pan, Hsien-Yu, Lin, Cheng-Han, Huang, Po-Yi, Lin, Kao-Cheng, Liaw, Jhon-Jhy, Chen, Yen-Huei, Liao, Hung-Jen, Chang, Jonathan
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
Get full text
Conference Proceeding
A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs
YEN HUEI CHEN, CHAN, Gary, SHAO YU CHOU, PAN, Hsien-Yu, WU, Jui-Jen, LEE, Robin, LIAO, H. J, YAMAUCHI, Hiroyuki
Published in IEEE journal of solid-state circuits (01.04.2009)
Published in IEEE journal of solid-state circuits (01.04.2009)
Get full text
Conference Proceeding
Journal Article
METHOD AND SYSTEM TO BALANCE GROUND BOUNCE
LIN CHIH YU, CHEN YEN HUEI, ZHAO WEI CHANG, PAN HSIEN YU, FUJIWARA HIDEHIRO
Year of Publication 13.12.2021
Get full text
Year of Publication 13.12.2021
Patent
MEMORY ARRAY CIRCUIT AND METHOD OF MANUFACTURING SAME
LIN CHIH YU, OKUNO YASUTOSHI, CHEN YEN HUEI, LIAO HUNG JEN, PAN HSIEN YU, FUJIWARA HIDEHIRO
Year of Publication 04.08.2021
Get full text
Year of Publication 04.08.2021
Patent
SRAM cell current in low leakage design
Ding-Ming Kwai, Ching-Hua Hsiao, Chung-Ping Kuo, Chi-Hsien Chuang, Min-Chung Hsu, Yi-Chun Chen, Yu-Ling Sung, Hsien-Yu Pan, Chia-Hsin Lee, Meng-Fan Chang, Yung-Fa Chou
Published in 2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06) (2006)
Published in 2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06) (2006)
Get full text
Conference Proceeding
SRAM VARIATION TOLERANT READ ASSIST CIRCUIT FOR SRAM
LIN CHIH YU, SINGH SAHIL PREET, CHEN YEN HUEI, LIAO HUNG JEN, PAN HSIEN YU, FUJIWARA HIDEHIRO
Year of Publication 08.07.2021
Get full text
Year of Publication 08.07.2021
Patent
METHOD AND SYSTEM TO BALANCE GROUND BOUNCE
LIN CHIH YU, CHEN YEN HUEI, ZHAO WEI CHANG, PAN HSIEN YU, FUJIWARA HIDEHIRO
Year of Publication 11.05.2020
Get full text
Year of Publication 11.05.2020
Patent
MEMORY ARRAY CIRCUIT AND METHOD OF MANUFACTURING SAME
LIN CHIH YU, OKUNO YASUTOSHI, CHEN YEN HUEI, LIAO HUNG JEN, PAN HSIEN YU, FUJIWARA HIDEHIRO
Year of Publication 28.01.2020
Get full text
Year of Publication 28.01.2020
Patent
MULTI WORD LINE ASSERTION
LIN CHIH YU, ZHAO WEI CHANG, CHEN YEN HUEI, PAN HSIEN YU, FUJIWARA HIDEHIRO
Year of Publication 26.12.2019
Get full text
Year of Publication 26.12.2019
Patent
STATIC RANDOM ACCESS MEMORY WITH WRITE ASSIST CIRCUIT
LIN CHIH YU, SINGH SAHIL PREET, CHEN YEN HUEI, LIAO HUNG JEN, PAN HSIEN YU, FUJIWARA HIDEHIRO
Year of Publication 26.10.2020
Get full text
Year of Publication 26.10.2020
Patent
SRAM VARIATION TOLERANT READ ASSIST CIRCUIT FOR SRAM
LIN CHIH YU, SINGH SAHIL PREET, CHEN YEN HUEI, LIAO HUNG JEN, PAN HSIEN YU, FUJIWARA HIDEHIRO
Year of Publication 08.01.2020
Get full text
Year of Publication 08.01.2020
Patent
MEMORY ARRAY CIRCUIT AND METHOD OF MANUFACTURING THE SAME
LIN CHIH YU, SINGH SAHIL PREET, CHEN YEN HUEI, LIAO HUNG JEN, PAN HSIEN YU, FUJIWARA HIDEHIRO
Year of Publication 08.03.2019
Get full text
Year of Publication 08.03.2019
Patent
STATIC RANDOM ACCESS MEMORY WITH WRITE ASSIST CIRCUIT
LIN CHIH YU, SINGH SAHIL PREET, CHEN YEN HUEI, LIAO HUNG JEN, PAN HSIEN YU, FUJIWARA HIDEHIRO
Year of Publication 11.02.2019
Get full text
Year of Publication 11.02.2019
Patent
MEMORY CELL
LIN CHIH YU, LIN CHIEN CHEN, LIAO HUNG JEN, CHEN YEN HUEI, PAN HSIEN YU, FUJIWARA HIDEHIRO
Year of Publication 08.06.2018
Get full text
Year of Publication 08.06.2018
Patent
LAYOUT SCHEME AND METHOD FOR FORMING DEVICE CELL IN SEMINCONDUCTOR DEVICES
CHEN JUNG HSUAN, CHOU SHAO YU, CHEN YEN HUEI, LIAO HUNG JEN, PAN HSIEN YU
Year of Publication 17.10.2012
Get full text
Year of Publication 17.10.2012
Patent
24.4 A 5nm 5.7GHz@1.0V and 1.3GHz@0.5V 4kb Standard-Cell- Based Two-Port Register File with a 16T Bitcell with No Half-Selection Issue
Fujiwara, Hidehiro, Nien, Yi-Hsin, Lin, Chih-Yu, Pan, Hsien-Yu, Hsu, Hao-Wen, Wu, Shin-Rung, Liu, Yao-Yi, Chen, Yen-Huei, Liao, Hung-Jen, Chang, Jonathan
Published in 2021 IEEE International Solid- State Circuits Conference (ISSCC) (13.02.2021)
Published in 2021 IEEE International Solid- State Circuits Conference (ISSCC) (13.02.2021)
Get full text
Conference Proceeding
A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDDmin VLSIs
Yen Huei Chen, Chan, G., Shao Yu Chou, Hsien-Yu Pan, Jui-Jen Wu, Lee, R., Liao, H.J., Yamauchi, H.
Published in IEEE journal of solid-state circuits (01.04.2009)
Published in IEEE journal of solid-state circuits (01.04.2009)
Get full text
Journal Article
Memory array circuit and method of manufacturing same
Fujiwara, Hidehiro, Lin, Chih-Yu, Chen, Yen-Huei, Okuno, Yasutoshi, Liao, Hung-Jen, Pan, Hsien-Yu
Year of Publication 02.07.2024
Get full text
Year of Publication 02.07.2024
Patent
METHOD AND SYSTEM TO BALANCE GROUND BOUNCE
Fujiwara, Hidehiro, Lin, Chih-Yu, Chen, Yen-Huei, Zhao, Wei-Chang, Pan, Hsien-Yu
Year of Publication 23.11.2023
Get full text
Year of Publication 23.11.2023
Patent
Memory array circuit and method of manufacturing same
Fujiwara, Hidehiro, Lin, Chih-Yu, Singh, Sahil Preet, Chen, Yen-Huei, Liao, Hung-Jen, Pan, Hsien-Yu
Year of Publication 27.08.2024
Get full text
Year of Publication 27.08.2024
Patent