Search Results - "PALASKAS, Yorgos" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

A 2.4-GHz 20-40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS

A 2.4-GHz 20-40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS

by Ravi, A., Madoglio, P., Hongtao Xu, Chandrashekar, K., Verhelst, M., Pellerano, S., Cuellar, L., Aguirre-Hernandez, M., Sajadieh, M., Zarate-Roldan, J. E., Bochobza-Degani, O., Lakdawala, H., Palaskas, Y.
Published in IEEE journal of solid-state circuits (01.12.2012)

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Journal Article Conference Proceeding

A mm-Wave Power-Harvesting RFID Tag in 90 nm CMOS

A mm-Wave Power-Harvesting RFID Tag in 90 nm CMOS

by Pellerano, Stefano, Alvarado, Javier, Palaskas, Yorgos
Published in IEEE journal of solid-state circuits (01.08.2010)

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Journal Article Conference Proceeding

A 39.1-to-41.6GHz ΔΣ Fractional-N Frequency Synthesizer in 90nm CMOS

A 39.1-to-41.6GHz ΔΣ Fractional-N Frequency Synthesizer in 90nm CMOS

by Pellerano, Stefano, Mukhopadhyay, Rajarshi, Ravi, Ashoke, Laskar, Joy, Palaskas, Yorgos
Published in 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers (01.02.2008)

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Conference Proceeding

A Cellular Multiband DTC-Based Digital Polar Transmitter With −153-dBc/Hz Noise in 14-nm FinFET

A Cellular Multiband DTC-Based Digital Polar Transmitter With −153-dBc/Hz Noise in 14-nm FinFET

by Madoglio, Paolo, Palaskas, Yorgos, Angel, Jorn, Tomasik, Jakob, Hampel, Sven, Schubert, Petra, Preyler, Peter, Mayer, Thomas, Bauernfeind, Thomas, Plechinger, Peter, Ravi, Ashoke, Degani, Ofir, Banin, Rotem, Gordon, Eshel, Martev, Dimo, Gossmann, Timo, Holm, Andreas, Boos, Zdravko
Published in IEEE journal of solid-state circuits (01.07.2020)

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Journal Article

A Transformer-Combined 31.5 dBm Outphasing Power Amplifier in 45 nm LP CMOS With Dynamic Power Control for Back-Off Power Efficiency Enhancement

A Transformer-Combined 31.5 dBm Outphasing Power Amplifier in 45 nm LP CMOS With Dynamic Power Control for Back-Off Power Efficiency Enhancement

by Wei Tai, Hongtao Xu, Ravi, A., Lakdawala, H., Bochobza-Degani, O., Carley, L. R., Palaskas, Y.
Published in IEEE journal of solid-state circuits (01.07.2012)

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Journal Article Conference Proceeding

A Flip-Chip-Packaged 25.3 dBm Class-D Outphasing Power Amplifier in 32 nm CMOS for WLAN Application

A Flip-Chip-Packaged 25.3 dBm Class-D Outphasing Power Amplifier in 32 nm CMOS for WLAN Application

by Hongtao Xu, Palaskas, Y., Ravi, A., Sajadieh, M., El-Tanani, M. A., Soumyanath, K.
Published in IEEE journal of solid-state circuits (01.07.2011)

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Journal Article

A 64 GHz LNA With 15.5 dB Gain and 6.5 dB NF in 90 nm CMOS

A 64 GHz LNA With 15.5 dB Gain and 6.5 dB NF in 90 nm CMOS

by Pellerano, S., Palaskas, Y., Soumyanath, K.
Published in IEEE journal of solid-state circuits (01.07.2008)

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Journal Article

A 4-GS/s 4-bit flash ADC in 0.18-μm CMOS

A 4-GS/s 4-bit flash ADC in 0.18-μm CMOS

by PARK, Sunghyun, PALASKAS, Yorgos, FLYNN, Michael P
Published in IEEE journal of solid-state circuits (2007)

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Journal Article

A Class-E PA With Pulse-Width and Pulse-Position Modulation in 65 nm CMOS

A Class-E PA With Pulse-Width and Pulse-Position Modulation in 65 nm CMOS

by Walling, J.S., Lakdawala, H., Palaskas, Y., Ravi, A., Degani, O., Soumyanath, K., Allstot, D.J.
Published in IEEE journal of solid-state circuits (01.06.2009)

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Journal Article

Transformer-Combining Digital PA with Efficiency Peaking at 0, −6, and −12 dB Backoff in 32nm CMOS

Transformer-Combining Digital PA with Efficiency Peaking at 0, −6, and −12 dB Backoff in 32nm CMOS

by Seddighrad, Parmoon, Palaskas, Yorgos, Xu, Hongtao, Madoglio, Paolo, Chandarshekar, Kailash, Allstot, David J.
Published in 2020 IEEE International Symposium on Circuits and Systems (ISCAS) (01.10.2020)

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Conference Proceeding

A 4.75-GHz Fractional Frequency Divider-by-1.25 With TDC-Based All-Digital Spur Calibration in 45-nm CMOS

A 4.75-GHz Fractional Frequency Divider-by-1.25 With TDC-Based All-Digital Spur Calibration in 45-nm CMOS

by Pellerano, S., Madoglio, P., Palaskas, Y.
Published in IEEE journal of solid-state circuits (01.12.2009)

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Journal Article

Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference

Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference

by Savoj, Jafar, Manoli, Yiannos, Darabi, Hooman, Palaskas, Yorgos, Moyal, Michael
Published in IEEE journal of solid-state circuits (01.12.2011)

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Journal Article

A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell Design With Time-Interleaving

A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell Design With Time-Interleaving

by Madoglio, Paolo, Ravi, Ashoke, Cuellar, Luis, Pellerano, Stefano, Seddighrad, Parmoon, Lomeli, Ismael, Palaskas, Yorgos
Published in IEEE journal of solid-state circuits (01.07.2010)

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Journal Article

Session 9 overview / wireless: Wireless & mm-Wave connectivity

Session 9 overview / wireless: Wireless & mm-Wave connectivity

by Burra, Gangadhar, Palaskas, Yorgos
Published in 2011 IEEE International Solid-State Circuits Conference (01.02.2011)

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Conference Proceeding

A 64 GHz LNA With 15.5 dB Gain and 6.5 dB NF in 90 nm CMOS: The 33rd European Solid-State Circuits Conference (ESSCIRC 2007)

A 64 GHz LNA With 15.5 dB Gain and 6.5 dB NF in 90 nm CMOS: The 33rd European Solid-State Circuits Conference (ESSCIRC 2007)

by PELLERANO, Stefano, PALASKAS, Yorgos, SOUMYANATH, Krishnamurthy
Published in IEEE journal of solid-state circuits (2008)

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Journal Article

Session 11 overview: radar, mm-Wave, & low-power transceivers

Session 11 overview: radar, mm-Wave, & low-power transceivers

by Palaskas, Yorgos, Ingels, Mark
Published in 2010 IEEE International Solid-State Circuits Conference - (ISSCC) (01.02.2010)

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Conference Proceeding

CHIP PACKAGES INCLUDING THROUGH-SILICON VIA DICE WITH VERTICALLY INTEGRATED PHASED-ARRAY ANTENNAS AND LOW-FREQUENCY AND POWER DELIVERY SUBSTRATES

CHIP PACKAGES INCLUDING THROUGH-SILICON VIA DICE WITH VERTICALLY INTEGRATED PHASED-ARRAY ANTENNAS AND LOW-FREQUENCY AND POWER DELIVERY SUBSTRATES

by PALASKAS YORGOS, KAMGAING TELESPHOR, RAO VALLURI R
Year of Publication 05.02.2014

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Patent

A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, [Delta][Sigma] Modulator Based on Standard Cell Design With Time-Interleaving

A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, [Delta][Sigma] Modulator Based on Standard Cell Design With Time-Interleaving

by Madoglio, Paolo, Ravi, Ashoke, Cuellar, Luis, Pellerano, Stefano, Seddighrad, Parmoon, Lomeli, Ismael, Palaskas, Yorgos
Published in IEEE journal of solid-state circuits (01.07.2010)

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Journal Article

A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, Delta capital sigma Modulator Based on Standard Cell Design With Time-Interleaving

A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, Delta capital sigma Modulator Based on Standard Cell Design With Time-Interleaving

by Madoglio, Paolo, Ravi, Ashoke, Cuellar, Luis, Pellerano, Stefano, Seddighrad, Parmoon, Lomeli, Ismael, Palaskas, Yorgos
Published in IEEE journal of solid-state circuits (01.07.2010)

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Journal Article

A highly linear 25dBm outphasing power amplifier in 32nm CMOS for WLAN application

A highly linear 25dBm outphasing power amplifier in 32nm CMOS for WLAN application

by Hongtao Xu, Palaskas, Yorgos, Ravi, Ashoke, Soumyanath, Krishnamurthy
Published in 2010 Proceedings of ESSCIRC (01.09.2010)

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Conference Proceeding