HetSched: Quality-of-Mission Aware Scheduling for Autonomous Vehicle SoCs
Amarnath, Aporva, Pal, Subhankar, Kassa, Hiwot, Vega, Augusto, Buyuktosunoglu, Alper, Franke, Hubertus, Wellman, John-David, Dreslinski, Ronald, Bose, Pradip
Year of Publication 24.03.2022
Year of Publication 24.03.2022
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Journal Article
Branch target filtering based on memory region access count
Kalamatianos, John, Yalavarti, Adithya, Agrawal, Varun, Srinivasan, Vinesh, Pal, Subhankar
Year of Publication 10.01.2023
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Year of Publication 10.01.2023
Patent
FILTERED BRANCH PREDICTION STRUCTURES OF A PROCESSOR
KALAMATIANOS, John, PAL, Subhankar, YALAVARTI, Adithya, SRINIVASAN, Vinesh, AGRAWAL, Varun
Year of Publication 03.08.2022
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Year of Publication 03.08.2022
Patent
HETSIM: Simulating Large-Scale Heterogeneous Systems using a Trace-driven, Synchronization and Dependency-Aware Framework
Pal, Subhankar, Kaszyk, Kuba, Feng, Siying, Franke, Bjorn, Cole, Murray, O'Boyle, Michael, Mudge, Trevor, Dreslinski, Ronald G.
Published in 2020 IEEE International Symposium on Workload Characterization (IISWC) (01.10.2020)
Published in 2020 IEEE International Symposium on Workload Characterization (IISWC) (01.10.2020)
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Conference Proceeding
STOMP: A Tool for Evaluation of Scheduling Policies in Heterogeneous Multi-Processors
Vega, Augusto, Amarnath, Aporva, Wellman, John-David, Kassa, Hiwot, Pal, Subhankar, Franke, Hubertus, Buyuktosunoglu, Alper, Dreslinski, Ronald, Bose, Pradip
Year of Publication 28.07.2020
Year of Publication 28.07.2020
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Journal Article
FILTERED BRANCH PREDICTION STRUCTURES OF A PROCESSOR
KALAMATIANOS, John, PAL, Subhankar, YALAVARTI, Adithya, SRINIVASAN, Vinesh, AGRAWAL, Varun
Year of Publication 30.06.2021
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Year of Publication 30.06.2021
Patent
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm
Kim, Sung, Fayazi, Morteza, Daftardar, Alhad, Chen, Kuan-Yu, Tan, Jielun, Pal, Subhankar, Ajayi, Tutu, Xiong, Yan, Mudge, Trevor, Chakrabarti, Chaitali, Blaauw, David, Dreslinski, Ronald, Kim, Hun-Seok
Published in 2021 Symposium on VLSI Circuits (13.06.2021)
Published in 2021 Symposium on VLSI Circuits (13.06.2021)
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Conference Proceeding
PACKING MACHINE LEARNING MODELS USING PRUNING AND PERMUTATION
PAL, Subhankar, BUYUKTOSUNOGLU, Alper, VACULIN, Roman, AHARONI, Ehud, SOCEANU, Omri, SARPATWAR, Kanthi, DRUCKER, Nir, SHAUL, Hayim, BARUCH, Moran, BOSE, Pradip
Year of Publication 11.01.2024
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Year of Publication 11.01.2024
Patent
PACKING MACHINE LEARNING MODELS USING PRUNING AND PERMUTATION
PAL, Subhankar, BUYUKTOSUNOGLU, Alper, VACULIN, Roman, AHARONI, Ehud, SOCEANU, Omri, SARPATWAR, Kanthi, DRUCKER, Nir, SHAUL, Hayim, BARUCH, Moran, BOSE, Pradip
Year of Publication 11.01.2024
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Year of Publication 11.01.2024
Patent
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm
Kim, Sung, Fayazi, Morteza, Daftardar, Alhad, Kuan-Yu, Chen, Tan, Jielun, Pal, Subhankar, Ajayi, Tutu, Xiong, Yan, Mudge, Trevor, Chakrabarti, Chaitali, Blaauw, David, Dreslinski, Ronald, Hun-Seok Kim
Published in arXiv.org (01.08.2021)
Published in arXiv.org (01.08.2021)
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Paper
Journal Article
NEURAL NETWORK INFERENCE UNDER HOMOMORPHIC ENCRYPTION
Vaculin, Roman, Soceanu, Omri, Aharoni, Ehud, Buyuktosunoglu, Alper, Bose, Pradip, Shaul, Hayim, Pal, Subhankar, Rayfield, James Thomas, Drucker, Nir, Sarpatwar, Kanthi
Year of Publication 01.08.2024
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Year of Publication 01.08.2024
Patent
FILTERED BRANCH PREDICTION STRUCTURES OF A PROCESSOR
KALAMATIANOS, John, PAL, Subhankar, YALAVARTI, Adithya, SRINIVASAN, Vinesh, AGRAWAL, Varun
Year of Publication 27.02.2020
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Year of Publication 27.02.2020
Patent
FILTERED BRANCH PREDICTION STRUCTURES OF A PROCESSOR
KALAMATIANOS, John, PAL, Subhankar, YALAVARTI, Adithya, SRINIVASAN, Vinesh, AGRAWAL, Varun
Year of Publication 27.02.2020
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Year of Publication 27.02.2020
Patent
Power Grid 2.0 - A journey from unified communication to unified grid
Pal, S.
Published in 2009 13th International Conference on Intelligence in Next Generation Networks (01.10.2009)
Published in 2009 13th International Conference on Intelligence in Next Generation Networks (01.10.2009)
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Conference Proceeding
A New Design of an N-Bit Reversible Arithmetic Logic Unit
Pal, Subhankar, Vudadha, Chetan, Phaneendra, P. Sai, Veeramachaneni, Sreehari, Mandalika, Srinivas
Published in 2014 Fifth International Symposium on Electronic System Design (01.12.2014)
Published in 2014 Fifth International Symposium on Electronic System Design (01.12.2014)
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Conference Proceeding
TSaaS - Customized telecom app hosting on cloud
Pal, S., Pal, T.
Published in 2011 IEEE 5th International Conference on Internet Multimedia Systems Architecture and Application (01.12.2011)
Published in 2011 IEEE 5th International Conference on Internet Multimedia Systems Architecture and Application (01.12.2011)
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Conference Proceeding
Filtered branch prediction structures of processor
YALAVARTI ADITHYA, PAL SUBHANKAR, KALAMATIANOS JOHN, AGRAWAL VARUN, SRINIVASAN VINESH
Year of Publication 30.03.2021
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Year of Publication 30.03.2021
Patent