A 50V input range 14bit 250kS/s ADC with 97.8dB SFDR and 80.2dB SNR
Ozkaya, Ilter, Gurleyuk, Cagri, Ergul, Atilim, Akkaya, Arda, Aksin, Devrim Yilmaz
Published in ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) (01.09.2014)
Published in ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) (01.09.2014)
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Conference Proceeding
A 24-72-GS/s 8-b Time-Interleaved SAR ADC With 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET
Kull, Lukas, Luu, Danny, Menolfi, Christian, Brandli, Matthias, Francese, Pier Andrea, Morf, Thomas, Kossel, Marcel, Cevrero, Alessandro, Ozkaya, Ilter, Toifl, Thomas
Published in IEEE journal of solid-state circuits (01.12.2018)
Published in IEEE journal of solid-state circuits (01.12.2018)
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Journal Article
A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET
Kim, Gain, Kossel, Marcel, Cevrero, Alessandro, Ozkaya, Ilter, Burg, Andreas, Toifl, Thomas, Leblebici, Yusuf, Kull, Lukas, Luu, Danny, Braendli, Matthias, Menolfi, Christian, Francese, Pier-Andrea, Yueksel, Hazar, Aprile, Cosimo, Morf, Thomas
Published in IEEE journal of solid-state circuits (01.01.2020)
Published in IEEE journal of solid-state circuits (01.01.2020)
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Journal Article
A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET
Luu, Danny, Kull, Lukas, Toifl, Thomas, Menolfi, Christian, Brandli, Matthias, Francese, Pier Andrea, Morf, Thomas, Kossel, Marcel, Yueksel, Hazar, Cevrero, Alessandro, Ozkaya, Ilter, Huang, Qiuting
Published in IEEE journal of solid-state circuits (01.11.2018)
Published in IEEE journal of solid-state circuits (01.11.2018)
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Journal Article
A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET
Ozkaya, Ilter, Cevrero, Alessandro, Francese, Pier Andrea, Menolfi, Christian, Morf, Thomas, Brandli, Matthias, Kuchta, Daniel M., Kull, Lukas, Baks, Christian W., Proesel, Jonathan E., Kossel, Marcel, Luu, Danny, Lee, Benjamin G., Doany, Fuad E., Meghelli, Mounir, Leblebici, Yusuf, Toifl, Thomas
Published in IEEE journal of solid-state circuits (01.12.2017)
Published in IEEE journal of solid-state circuits (01.12.2017)
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Journal Article
A 32 Gb/s, 4.7 pJ/bit Optical Link With −11.7 dBm Sensitivity in 14-nm FinFET CMOS
Proesel, Jonathan E., Toprak-Deniz, Zeynep, Cevrero, Alessandro, Ozkaya, Ilter, Kim, Seongwon, Kuchta, Daniel M., Lee, Sungjae, Rylov, Sergey V., Ainspan, Herschel, Dickson, Timothy O., Bulzacchelli, John F., Meghelli, Mounir
Published in IEEE journal of solid-state circuits (01.04.2018)
Published in IEEE journal of solid-state circuits (01.04.2018)
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Journal Article
A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS
Menolfi, Christian, Toifl, Thomas, Braendli, Matthias, Francese, Pier Andrea, Morf, Thomas, Cevrero, Alessandro, Kossel, Marcel, Kull, Lukas, Luu, Danny, Ozkaya, Ilter
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01.02.2018)
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01.02.2018)
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Conference Proceeding
Design considerations for 50G+ backplane links
Toifl, Thomas, Brandli, Matthias, Cevrero, Alessandro, Francese, Pier Andrea, Kossel, Marcel, Kull, Lukas, Luu, Danny, Menolfi, Christian, Morf, Thomas, Ozkaya, Ilter, Yueksel, Hazar
Published in ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference (01.09.2016)
Published in ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference (01.09.2016)
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Conference Proceeding
A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET
Ozkaya, Ilter, Cevrero, Alessandro, Francese, Pier Andrea, Menolfi, Christian, Morf, Thomas, Brandli, Matthias, Kuchta, Daniel M., Kull, Lukas, Baks, Christian W., Proesel, Jonathan E., Kossel, Marcel, Luu, Danny, Lee, Benjamin G., Doany, Fuad E., Meghelli, Mounir, Leblebici, Yusuf, Toifl, Thomas
Published in IEEE journal of solid-state circuits (01.04.2018)
Published in IEEE journal of solid-state circuits (01.04.2018)
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Journal Article
A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET
Kull, Lukas, Luu, Danny, Menolfi, Christian, Braendli, Matthias, Francese, Pier Andrea, Morf, Thomas, Kossel, Marcel, Cevrero, Alessandro, Ozkaya, Ilter, Toifl, Thomas
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01.02.2018)
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01.02.2018)
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Conference Proceeding
6.1 A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET
Cevrero, Alessandro, Ozkaya, Ilter, Francese, Pier Andrea, Brandli, Matthias, Menolfi, Christian, Morf, Thomas, Kossel, Marcel, Kull, Lukas, Luu, Danny, Dazzi, Martino, Toifl, Thomas
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
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Conference Proceeding
A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS
Ozkaya, Ilter, Cevrero, Alessandro, Francese, Pier Andrea, Menolfi, Christian, Braendli, Matthias, Morf, Thomas, Kuchta, Dan, Kull, Lukas, Kossel, Marcel, Luu, Danny, Meghelli, Mounir, Leblebici, Yusuf, Toifl, Thomas
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01.02.2018)
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01.02.2018)
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Conference Proceeding
30.2 A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET
Kim, Gain, Kull, Lukas, Luu, Danny, Braendli, Matthias, Menolfi, Christian, Francese, Pier-Andrea, Yueksel, Hazar, Aprile, Cosimo, Morf, Thomas, Kossel, Marcel, Cevrero, Alessandro, Ozkaya, Ilter, Burg, Andreas, Toifl, Thomas, Leblebici, Yusuf
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
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Conference Proceeding
Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver
Gain Kim, Kull, Lukas, Luu, Danny, Braendli, Matthias, Menolfi, Christian, Francese, Pier Andrea, Aprile, Cosimo, Morf, Thomas, Kossel, Marcel, Cevrero, Alessandro, Ozkaya, Ilter, Toifl, Thomas, Leblebici, Yusuf
Published in 2018 IEEE International Symposium on Circuits and Systems (ISCAS) (27.05.2018)
Published in 2018 IEEE International Symposium on Circuits and Systems (ISCAS) (27.05.2018)
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Conference Proceeding
28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET
Kull, Lukas, Luu, Danny, Menolfi, Christian, Braendli, Matthias, Francese, Pier Andrea, Morf, Thomas, Kossel, Marcel, Yueksel, Hazar, Cevrero, Alessandro, Ozkaya, Ilter, Toifl, Thomas
Published in 2017 IEEE International Solid-State Circuits Conference (ISSCC) (01.02.2017)
Published in 2017 IEEE International Solid-State Circuits Conference (ISSCC) (01.02.2017)
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Conference Proceeding
29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET
Cevrero, Alessandro, Ozkaya, Ilter, Francese, Pier Andrea, Menolfi, Christian, Morf, Thomas, Brandli, Matthias, Kuchta, Dan, Kull, Lukas, Proesel, Jon, Kossel, Marcel, Luu, Danny, Lee, Benjamin, Doany, Fuad, Meghelli, Mounir, Leblebici, Yusuf, Toifl, Thomas
Published in 2017 IEEE International Solid-State Circuits Conference (ISSCC) (01.02.2017)
Published in 2017 IEEE International Solid-State Circuits Conference (ISSCC) (01.02.2017)
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Conference Proceeding
A 10-Bit 20-40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration
Kull, Lukas, Luu, Danny, Menolfi, Christian, Morf, Thomas, Francese, Pier Andrea, Braendli, Matthias, Kossel, Marcel, Cevrero, Alessandro, Ozkaya, Ilter, Toifl, Thomas
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
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Conference Proceeding
A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE
Francese, Pier Andrea, Cevrero, Alessandro, Ozkaya, Ilter, Brandli, Matthias, Menolfi, Christian, Morf, Thomas, Kossel, Marcel, Kull, Lukas, Luu, Danny, Toifl, Thomas
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
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Conference Proceeding