Search Results - "Orenstein Doron" :: K.UTB vyhledávací portál

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Mathematical modeling of tech-related real-world problems for secondary school-level mathematics

by Kohen, Zehavit, Orenstein, Doron
Published in Educational studies in mathematics (01.05.2021)

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Journal Article

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A NEW INSTRUCTION AND HIGHLY EFFICIENT MICRO-ARCHITECTURE TO ENABLE INSTANT CONTEXT SWITCH FOR USER-LEVEL THREADING

by ORENSTEIN DORON
Year of Publication 19.03.2015

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Patent

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UNPACKING PACKED DATA IN MULTIPLE LANES

by ORENSTEIN DORON, HARGIL ASAF
Year of Publication 16.03.2012

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Patent

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METHOD AND DEVICE FOR VARYING ENERGY PER INSTRUCTION ACCORDING TO AMOUNT OF AVAILABLE PARALLELISM

by ANNAVARAM MURALI, GROCHOWSKI EDWARD, SHEAFFER GAD, SHEN JOHN, WANG HONG, ORENSTEIN DORON, RONEN RONNY
Year of Publication 12.05.2016

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Patent

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SYSTEM FOR VARYING ENERGY PER INSTRUCTION ACCORDING TO AMOUNT OF AVAILABLE PARALLELISM

by ANNAVARAM MURALI, GROCHOWSKI EDWARD, SHEAFFER GAD, SHEN JOHN, WANG HONG, ORENSTEIN DORON, RONEN RONNY
Year of Publication 12.02.2015

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Patent

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INSTRUCTION AND LOGIC FOR PERFORMING RANGE DETECTION

by MYASKOUVSKEY ARTIOM, ORENSTEIN DORON, FIKSMAN EVGENY, HARGIL ASAF
Year of Publication 11.05.2010

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Patent

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A new instruction and highly efficient micro-architecture to enable instant context switch for user-level threading

by ORENSTEIN DORON
Year of Publication 06.05.2015

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Patent

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A new instruction and highly efficent micro-architecture to enable instant context switch for user-level threading

by DORON ORENSTEIN
Year of Publication 15.04.2015

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Patent

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Compressed instruction format

by Toll, Bret L, Valentine, Robert, Orenstein, Doron
Year of Publication 29.06.2021

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Patent

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INSTRUCTION AND HIGHLY EFFICIENT MICRO-ARCHITECTURE TO ENABLE INSTANT CONTEXT SWITCH FOR USER-LEVEL THREADING

by ORENSTEIN DORON
Year of Publication 03.04.2014

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Patent

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A NEW INSTRUCTION AND HIGHLY EFFICIENT MICRO-ARCHITECTURE TO ENABLE INSTANT CONTEXT SWITCH FOR USER-LEVEL THREADING

by ORENSTEIN, DORON
Year of Publication 03.04.2014

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Patent

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COMPRESSED INSTRUCTION FORMAT

by Toll, Bret L, Valentine, Robert, Orenstein, Doron
Year of Publication 10.10.2019

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Patent

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Unpacking packed data in multiple lanes

by ORENSTEIN DORON, HARGIL ASAF
Year of Publication 21.07.2015

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Patent

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Unpacking packed data in multiple lanes

by ORENSTEIN DORON, HARGIL ASAF
Year of Publication 14.07.2015

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Patent

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In-lane vector shuffle instructions

by Eitan, Benny, Valentine, Robert, Sperber, Zeev, Orenstein, Doron
Year of Publication 10.11.2020

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Patent

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Unpacking packed data in multiple lanes

by ASAF HARGIL, DORON ORENSTEIN
Year of Publication 20.05.2015

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Patent

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Compressed instruction format

by Toll, Bret L, Valentine, Robert, Orenstein, Doron
Year of Publication 09.10.2018

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Patent

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In-lane vector shuffle instructions

by Eitan, Benny, Valentine, Robert, Sperber, Zeev, Orenstein, Doron
Year of Publication 24.12.2019

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Patent

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In-lane vector shuffle instructions

by Eitan, Benny, Valentine, Robert, Sperber, Zeev, Orenstein, Doron
Year of Publication 24.12.2019

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Patent

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In-lane vector shuffle instructions

by Eitan, Benny, Valentine, Robert, Sperber, Zeev, Orenstein, Doron
Year of Publication 24.12.2019

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Patent

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