Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems
Chen Kong Teh, Hamada, M., Fujita, T., Hara, H., Ikumi, N., Oowaki, Y.
Published in IEEE transactions on very large scale integration (VLSI) systems (01.12.2006)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.12.2006)
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A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling
Fujiyoshi, T., Shiratake, S., Nomura, S., Nishikawa, T., Kitasho, Y., Arakida, H., Okuda, Y., Tsuboi, Y., Hamada, M., Hara, H., Fujita, T., Hatori, F., Shimazawa, T., Yahagi, K., Takeda, H., Murakata, M., Minami, F., Kawabe, N., Kitahara, T., Seta, K., Takahashi, M., Oowaki, Y., Furuyama, T.
Published in IEEE journal of solid-state circuits (01.01.2006)
Published in IEEE journal of solid-state circuits (01.01.2006)
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A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive
Takashima, D., Shuto, S., Kunishima, I., Takenaka, H., Oowaki, Y., Tanaka, S.
Published in IEEE journal of solid-state circuits (01.11.1999)
Published in IEEE journal of solid-state circuits (01.11.1999)
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Sub-0.1 mu m circuit design with substrate-over-biasing
Oowaki, Y, Noguchi, M, Takagi, S, Takashima, D, Ono, M, Matsunaga, Y, Sunouchi, K, Kawaguchiya, H, Matsuda, S, Kamoshida, M, Fuse, T, Watanabe, S, Toriumi, A, Manabe, S, Hojo, A
Published in Digest of technical papers - IEEE International Solid-State Circuits Conference (01.01.1998)
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Published in Digest of technical papers - IEEE International Solid-State Circuits Conference (01.01.1998)
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Back gate effects on threshold voltage sensitivity to SOI thickness in fully-depleted SOI MOSFETs
Noguchi, M., Numata, T., Mitani, Y., Shino, T., Kawanaka, S., Oowaki, Y., Toriumi, A.
Published in IEEE electron device letters (01.01.2001)
Published in IEEE electron device letters (01.01.2001)
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A novel circuit technology with surrounding gate transistors (SGT's) for ultra high density DRAM's
Watanabe, S., Tsuchida, K., Takashima, D., Oowaki, Y., Nitayama, A., Hieda, K., Takato, H., Sunouchi, K., Horiguchi, F., Ohuchi, K., Masuoka, F., Hara, H.
Published in IEEE journal of solid-state circuits (01.09.1995)
Published in IEEE journal of solid-state circuits (01.09.1995)
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Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI's
Takashima, D., Oowaki, Y., Watanabe, S., Ohuchi, K.
Published in IEEE journal of solid-state circuits (01.02.1998)
Published in IEEE journal of solid-state circuits (01.02.1998)
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Journal Article
A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI
Hamada, M., Hara, H., Fujita, T., Chen Kong Teh, Shimazawa, T., Kawabe, N., Kitahara, T., Kikuchi, Y., Nishikawa, T., Takahashi, M., Oowaki, Y.
Published in Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005 (2005)
Published in Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005 (2005)
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Conference Proceeding
Standby/active mode logic for sub-1-V operating ULSI memory
Takashima, D., Watanabe, S., Nakano, H., Oowaki, Y., Ohuchi, K., Tango, H.
Published in IEEE journal of solid-state circuits (01.04.1994)
Published in IEEE journal of solid-state circuits (01.04.1994)
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An experimental DRAM with a NAND-structured cell
Hasegawa, T., Takashima, D., Ogiwara, R., Ohta, M., Shiratake, S.-I., Hamamoto, T., Yamada, T., Aoki, M., Ishibashi, S., Oowaki, Y., Watanabe, S., Masuoka, F.
Published in IEEE journal of solid-state circuits (01.11.1993)
Published in IEEE journal of solid-state circuits (01.11.1993)
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Conference Proceeding
A 33-ns 64-Mb DRAM
Oowaki, Y., Tsuchida, K., Watanabe, Y., Takashima, D., Ohta, M., Nakano, H., Watanabe, S., Nitayama, A., Horiguchi, F., Ohuchi, K., Masuoka, F.
Published in IEEE journal of solid-state circuits (01.11.1991)
Published in IEEE journal of solid-state circuits (01.11.1991)
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Journal Article
Word-line architecture for highly reliable 64-Mb DRAM
Takashima, D., Oowaki, Y., Ogiwara, R., Watanabe, Y., Tsuchida, K., Ohta, M., Nakano, H., Watanabe, S., Ohuchi, K.
Published in IEEE journal of solid-state circuits (01.04.1992)
Published in IEEE journal of solid-state circuits (01.04.1992)
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A 10.4pJ/b (32, 8) LDPC decoder with time-domain analog and digital mixed-signal processing
Miyashita, D., Yamaki, R., Hashiyoshi, K., Kobayashi, H., Kousai, S., Oowaki, Y., Unekawa, Y.
Published in 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (01.02.2013)
Published in 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (01.02.2013)
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Conference Proceeding
Open/folded bit-line arrangement for ultra-high-density DRAM's
Takashima, D., Watanabe, S., Nakano, H., Oowaki, Y., Ohuchi, K.
Published in IEEE journal of solid-state circuits (01.04.1994)
Published in IEEE journal of solid-state circuits (01.04.1994)
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Journal Article
New nibbled-page architecture for high-density DRAMs
Numata, K., Oowaki, Y., Itoh, Y., Hara, T., Tsuchida, K., Ohta, M., Watanabe, S., Ohuchi, K.
Published in IEEE journal of solid-state circuits (01.08.1989)
Published in IEEE journal of solid-state circuits (01.08.1989)
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The stabilized reference-line (SRL) technique for scaled DRAMs
Tsuchida, K., Oowaki, Y., Ohta, M., Takashima, D., Watanabe, S., Ohuchi, K., Masuoka, F.
Published in IEEE journal of solid-state circuits (01.02.1990)
Published in IEEE journal of solid-state circuits (01.02.1990)
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VIB-1 new hot-carrier-induced degradation phenomena in half-micrometer MOS transistors
Nitayama, A., Takenouchi, N., Hamamoto, T., Oowaki, Y.
Published in IEEE transactions on electron devices (01.11.1987)
Published in IEEE transactions on electron devices (01.11.1987)
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Session 2 overview - non-volatile memory
Sofer, Y., Oowaki, Y.
Published in ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005 (2005)
Published in ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005 (2005)
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Conference Proceeding
An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode
Watanabe, S., Oowaki, Y., Itoh, Y., Sakui, K., Numata, K., Fuse, T., Kobayashi, T., Tsuchida, K., Chiba, M., Hara, T., Ohta, M., Horiguchi, F., Hieda, K., Mitayama, A., Hamamoto, T., Ohuchi, K., Masuoka, F.
Published in IEEE journal of solid-state circuits (01.06.1989)
Published in IEEE journal of solid-state circuits (01.06.1989)
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