SC-DDPL: A Novel Standard-Cell Based Approach for Counteracting Power Analysis Attacks in the Presence of Unbalanced Routing
Bellizia, Davide, Bongiovanni, Simone, Olivieri, Mauro, Scotti, Giuseppe
Published in IEEE transactions on circuits and systems. I, Regular papers (01.07.2020)
Published in IEEE transactions on circuits and systems. I, Regular papers (01.07.2020)
Get full text
Journal Article
Dynamic Triple Modular Redundancy in Interleaved Hardware Threads: An Alternative Solution to Lockstep Multi-Cores for Fault-Tolerant Systems
Barbirotta, Marcello, Menichelli, Francesco, Cheikh, Abdallah, Mastrandrea, Antonio, Angioli, Marco, Olivieri, Mauro
Published in IEEE access (2024)
Published in IEEE access (2024)
Get full text
Journal Article
Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core
Barbirotta, Marcello, Cheikh, Abdallah, Mastrandrea, Antonio, Menichelli, Francesco, Ottavi, Marco, Olivieri, Mauro
Published in Journal of low power electronics and applications (01.03.2023)
Published in Journal of low power electronics and applications (01.03.2023)
Get full text
Journal Article
Optimal transistor sizing for maximum yield in variation-aware standard cell design
Abbas, Zia, Olivieri, Mauro
Published in International journal of circuit theory and applications (01.07.2016)
Published in International journal of circuit theory and applications (01.07.2016)
Get full text
Journal Article
Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme
Angioli, Marco, Barbirotta, Marcello, Cheikh, Abdallah, Mastrandrea, Antonio, Menichelli, Francesco, Jamili, Saeid, Olivieri, Mauro
Published in IEEE transactions on computers (01.07.2024)
Published in IEEE transactions on computers (01.07.2024)
Get full text
Journal Article
Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops
Khalid, Usman, Mastrandrea, Antonio, Olivieri, Mauro
Published in Microelectronics and reliability (01.12.2015)
Published in Microelectronics and reliability (01.12.2015)
Get full text
Journal Article
Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores
Cheikh, Abdallah, Sordillo, Stefano, Mastrandrea, Antonio, Menichelli, Francesco, Scotti, Giuseppe, Olivieri, Mauro
Published in IEEE MICRO (01.03.2021)
Published in IEEE MICRO (01.03.2021)
Get full text
Journal Article
Customizable Vector Acceleration in Extreme-Edge Computing: A RISC-V Software/Hardware Architecture Study on VGG-16 Implementation
Sordillo, Stefano, Cheikh, Abdallah, Mastrandrea, Antonio, Menichelli, Francesco, Olivieri, Mauro
Published in Electronics (Basel) (23.02.2021)
Published in Electronics (Basel) (23.02.2021)
Get full text
Journal Article
The international race towards Exascale in Europe
Gagliardi, Fabrizio, Moreto, Miquel, Olivieri, Mauro, Valero, Mateo
Published in CCF transactions on high performance computing (Online) (06.05.2019)
Published in CCF transactions on high performance computing (Online) (06.05.2019)
Get full text
Journal Article
A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design
Barbirotta, Marcello, Cheikh, Abdallah, Mastrandrea, Antonio, Menichelli, Francesco, Vigli, Francesco, Olivieri, Mauro
Published in 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (06.10.2021)
Published in 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (06.10.2021)
Get full text
Conference Proceeding
FAUST: Design and implementation of a pipelined RISC-V vector floating-point unit
Kovač, Mate, Dragić, Leon, Malnar, Branimir, Minervini, Francesco, Palomar, Oscar, Rojas, Carlos, Olivieri, Mauro, Knezović, Josip, Kovač, Mario
Published in Microprocessors and microsystems (01.03.2023)
Published in Microprocessors and microsystems (01.03.2023)
Get full text
Journal Article