A 32-Mb chain FeRAM with segment/stitch array architecture
Shiratake, S., Miyakawa, T., Takeuchi, Y., Ogiwara, R., Kamoshida, M., Hoya, K., Oikawa, K., Ozaki, T., Kunishima, I., Yamakawa, K., Sugimoto, S., Takashima, D., Joachim, H.-O., Rehm, N., Wohlfahrt, J., Nagel, N., Beitel, G., Jacob, M., Roehr, T.
Published in IEEE journal of solid-state circuits (01.11.2003)
Published in IEEE journal of solid-state circuits (01.11.2003)
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Journal Article
FRAM cell design with high immunity to fatigue and imprint for 0.5 μm 3 V 1T1C 1 Mbit FRAM
Tanaka, S., Ogiwara, R., Itoh, Y., Miyakawa, T., Takeuchi, Y., Doumae, S., Takenaka, H., Kamata, H.
Published in IEEE transactions on electron devices (01.04.2000)
Published in IEEE transactions on electron devices (01.04.2000)
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Journal Article
A 32Mb chain FeRAM with segment/stitch array architecture
Shiratake, S., Miyakawa, T., Takeuchi, Y., Ogiwara, R., Kamoshida, M., Hoya, K., Oikawa, K., Ozaki, T., Kunishima, I., Yamakawa, K., Sugimoto, S., Takashima, D., Joachim, H.O., Rehm, N., Wohlfahrt, J., Nagel, N., Beitel, G., Jacob, M., Roehr, T.
Published in 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC (2003)
Published in 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC (2003)
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Conference Proceeding
A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes
Shiga, H., Takashima, D., Shiratake, S., Hoya, K., Miyakawa, T., Ogiwara, R., Fukuda, R., Takizawa, R., Hatsuda, K., Matsuoka, F., Nagadomi, Y., Hashimoto, D., Nishimura, H., Hioka, T., Doumae, S., Shimizu, S., Kawano, M., Taguchi, T., Watanabe, Y., Fujii, S., Ozaki, T., Kanaya, H., Kumura, Y., Shimojo, Y., Yamada, Y., Minami, Y., Shuto, S., Yamakawa, K., Yamazaki, S., Kunishima, I., Hamamoto, T., Nitayama, A., Furuyama, T.
Published in IEEE journal of solid-state circuits (01.01.2010)
Published in IEEE journal of solid-state circuits (01.01.2010)
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Journal Article
Conference Proceeding
An experimental DRAM with a NAND-structured cell
Hasegawa, T., Takashima, D., Ogiwara, R., Ohta, M., Shiratake, S.-I., Hamamoto, T., Yamada, T., Aoki, M., Ishibashi, S., Oowaki, Y., Watanabe, S., Masuoka, F.
Published in IEEE journal of solid-state circuits (01.11.1993)
Published in IEEE journal of solid-state circuits (01.11.1993)
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Journal Article
Conference Proceeding
A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode
Hoya, Katsuhiko, Takashima, D, Shiratake, S, Ogiwara, R, Miyakawa, T, Shiga, H, Doumae, S M, Ohtsuki, S, Kumura, Y, Shuto, S, Ozaki, T, Yamakawa, K, Kunishima, I, Nitayama, A, Fujii, S
Published in IEEE transactions on very large scale integration (VLSI) systems (01.12.2010)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.12.2010)
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Journal Article
A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs
Takashima, D., Shiga, H., Hashimoto, D., Miyakawa, T., Shiratake, S., Hoya, K., Ogiwara, R., Takizawa, R., Doumae, S., Fukuda, R., Watanabe, Y., Fujii, S., Ozaki, T., Kanaya, H., Shuto, S., Yamakawa, K., Kunishima, I., Hamamoto, T., Nitayama, A.
Published in IEEE journal of solid-state circuits (01.09.2011)
Published in IEEE journal of solid-state circuits (01.09.2011)
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Journal Article
Word-line architecture for highly reliable 64-Mb DRAM
Takashima, D., Oowaki, Y., Ogiwara, R., Watanabe, Y., Tsuchida, K., Ohta, M., Nakano, H., Watanabe, S., Ohuchi, K.
Published in IEEE journal of solid-state circuits (01.04.1992)
Published in IEEE journal of solid-state circuits (01.04.1992)
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Journal Article
Induced hypotension for craniofacial surgery
Ogiwara, R, Suzuki, M, Shimizu, R
Published in Masui. The Japanese journal of anesthesiology (01.06.1988)
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Published in Masui. The Japanese journal of anesthesiology (01.06.1988)
Journal Article
A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes
Shiga, H., Takashima, D., Shiratake, S., Hoya, K., Miyakawa, T., Ogiwara, R., Fukuda, R., Takizawa, R., Hatsuda, K., Matsuoka, F., Nagadomi, Y., Hashimoto, D., Nishimura, H., Hioka, T., Doumae, S., Shimizu, S., Kawano, M., Taguchi, T., Watanabe, Y., Fujii, S., Ozaki, T., Kanaya, H., Kumura, Y., Shimojo, Y., Yamada, Y., Minami, Y., Shuto, S., Yamakawa, K., Yamazaki, S., Kunishima, I., Hamamoto, T., Nitayama, A., Furuyama, T.
Published in 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers (01.02.2009)
Published in 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers (01.02.2009)
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Conference Proceeding
A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM
Takashima, D., Shiga, H., Hashimoto, D., Miyakawa, T., Shiratake, S., Hoya, K., Ogiwara, R., Takizawa, R., Doumae, S., Fukuda, R., Watanabe, Y., Fujii, S., Ozaki, T., Kanaya, H., Shuto, S., Yamakawa, K., Kunishima, I., Hamamoto, T., Nitayama, A.
Published in 2010 IEEE International Solid-State Circuits Conference - (ISSCC) (01.02.2010)
Published in 2010 IEEE International Solid-State Circuits Conference - (ISSCC) (01.02.2010)
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Conference Proceeding
A 76-mm(2) 8-Mb chain ferroelectric memory
Takashima, D, Takeuchi, Y, Miyakawa, T, Itoh, Y, Ogiwara, R, Kamoshida, M, Hoya, K, Doumae, S M, Ozaki, T, Kanaya, H, Yamakawa, K, Kunishima, I, Oowaki, Y
Published in IEEE journal of solid-state circuits (01.11.2001)
Published in IEEE journal of solid-state circuits (01.11.2001)
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Journal Article
FRAM cell design with high immunity to fatigue and imprint for 0.5mu m 3 V 1T1C 1 Mbit FRAM
Tanaka, S, Ogiwara, R, Itoh, Y, Miyakawa, T, Takeuchi, Y, Doumae, S, Takenaka, H, Kamata, H
Published in IEEE transactions on electron devices (01.04.2000)
Published in IEEE transactions on electron devices (01.04.2000)
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Journal Article
FRAM cell design with high immunity to fatigue and imprint for 0.5 /spl mu/m 3 V 1T1C 1 Mbit FRAM
Tanaka, S., Ogiwara, R., Itoh, Y., Miyakawa, T., Takeuchi, Y., Doumae, S., Takenaka, H., Kamata, H.
Published in IEEE transactions on electron devices (01.04.2000)
Published in IEEE transactions on electron devices (01.04.2000)
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Journal Article
A 76-mm/sup 2/ 8-Mb chain ferroelectric memory
Takashima, D., Takeuchi, Y., Miyakawa, T., Itoh, Y., Ogiwara, R., Kamoshida, M., Hoya, K., Doumae, S.M., Ozaki, T., Kanaya, H., Yamakawa, K., Kunishima, I., Oowaki, Y.
Published in IEEE journal of solid-state circuits (01.11.2001)
Published in IEEE journal of solid-state circuits (01.11.2001)
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Journal Article
A 76-mm2 8-Mb chain ferroelectric memory
Takashima, D, Takeuchi, Y, Miyakawa, T, Itoh, Y, Ogiwara, R, Kamoshida, M, Hoya, K, Doumae, S.M, Ozaki, T, Kanaya, H, Yamakawa, K, Kunishima, I, Oowaki, Y
Published in IEEE journal of solid-state circuits (01.11.2001)
Published in IEEE journal of solid-state circuits (01.11.2001)
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Journal Article
0.5- mu m, 3-V, 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor
Ogiwara, Ryu, Tanaka, Sumio, Itoh, Yasuo, Miyakawa, Tadashi, Takeuchi, Yoshiaki, Doumae, Sumiko Mano, Takenaka, Hiroyuki, Kunishima, Iwao, Shuto, Susumu, Hidaka, Osamu, Ohtsuki, Sumito, Tanaka, Shin-ichi
Published in IEEE journal of solid-state circuits (2000)
Published in IEEE journal of solid-state circuits (2000)
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Journal Article
Développement d'un système d'isolation pour réservoir de navire de transport de gaz liquéfié équipé de réservoirs sphériques
OGIWARA, R, YOSHIDA, S, HASHIGUCHI, H, UENO, K, NAKAMURA, M, MURAO, K, HARADA, T
Published in Journal of the Society of Naval Architects of Japan (1983)
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Published in Journal of the Society of Naval Architects of Japan (1983)
Journal Article
A 76-mm super(2) 8-Mb chain ferroelectric memory
Takashima, D, Takeuchi, T, Miyakawa, T, Itoh, Y, Ogiwara, R, Kamoshida, M, Hoya, K, Doumae, S M, Ozaki, T, Kanaya, H, Yamakawa, K, Kunishima, I, Oowaki, Y
Published in IEEE journal of solid-state circuits (01.11.2001)
Published in IEEE journal of solid-state circuits (01.11.2001)
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Journal Article
A 0.5-/spl mu/m, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor
Ogiwara, R., Tanaka, S., Itoh, Y., Miyakawa, T., Takeuchi, Y., Doumae, S.M., Takenaka, H., Kunishima, I., Shuto, S., Hidaka, O., Ohtsuki, S.
Published in IEEE journal of solid-state circuits (01.04.2000)
Published in IEEE journal of solid-state circuits (01.04.2000)
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Journal Article