A 1-Tb 4-b/cell 4-Plane 162-Layer 3-D Flash Memory With 2.4-Gb/s IO Interface
Yuh, Jong Hak, Li, Yen-Lung Jason, Li, Heguang, Oyama, Yoshihiro, Hsu, Cynthia, Anantula, Pradeep, Jeong, Gwang Yeong Stanley, Amarnath, Anirudh, Darne, Siddhesh, Bhatia, Sneha, Tang, Tianyu, Arya, Aditya, Rastogi, Naman, Ookuma, Naoki, Mizukoshi, Hiroyuki, Yap, Alex, Wang, Demin, Kim, Steve, Wu, Yonggang, Peng, Min, Lu, Jason, Ip, Tommy, Malhotra, Seema, Han, Taekeun, Okumura, Masatoshi, Liu, Jiwen, Sohn, Jeongduk John, Chibvongodze, Hardwell, Balaga, Muralikrishna, Matsuda, Akihiro, Chen, Chen, K. V., Indra, G., V. S. N. K. Chaitanya, Ramachandra, Venky, Kato, Yosuke, Kumar, Ravi J., Wang, Huijuan, Moogat, Farookh, Yoon, In-Soo, Kanda, Kazushige, Shimizu, Takahiro, Shibata, Noboru, Yanagidaira, Kosuke, Kodama, Takuyo, Fukuda, Ryo, Hirashima, Yasuhiro, Abe, Mitsuhiro
Published in IEEE journal of solid-state circuits (01.01.2023)
Published in IEEE journal of solid-state circuits (01.01.2023)
Get full text
Journal Article
13.5 A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology
Siau, Chang, Kim, Kwang-Ho, Lee, Seungpil, Isobe, Katsuaki, Shibata, Noboru, Verma, Kapil, Ariki, Takuya, Li, Jason, Yuh, Jong, Amarnath, Anirudh, Nguyen, Qui, Kwon, Ohwon, Jeong, Stanley, Li, Heguang, Hsu, Hua-Ling, Tseng, Tai-yuan, Choi, Steve, Darne, Siddhesh, Anantula, Pradeep, Yap, Alex, Chibvongodze, Hardwell, Miwa, Hitoshi, Yamashita, Minoru, Watanabe, Mitsuyuki, Hayashi, Koichiro, Kato, Yosuke, Miwa, Toru, Kang, Jang Yong, Okumura, Masatoshi, Ookuma, Naoki, Balaga, Muralikrishna, Ramachandra, Venky, Matsuda, Aki, Kulkani, Swaroop, Rachineni, Raghavendra, Manjunath, Pai K., Takehara, Masahito, Pai, Anil, Rajendra, Srinivas, Hisada, Toshiki, Fukuda, Ryo, Tokiwa, Naoya, Kawaguchi, Kazuaki, Yamaoka, Masashi, Komai, Hiromitsu, Minamoto, Takatoshi, Unno, Masaki, Ozawa, Susumu, Nakamura, Hiroshi, Hishida, Tomoo, Kajitani, Yasuyuki, Lin, Lei
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
Get full text
Conference Proceeding
30.4 A 1Tb 3b/Cell 3D-Flash Memory in a 170+ Word-Line-Layer Technology
Higuchi, Tsutomu, Kodama, Takuyo, Kato, Koji, Fukuda, Ryo, Tokiwa, Naoya, Abe, Mitsuhiro, Takagiwa, Teruo, Shimizu, Yuki, Musha, Junji, Sakurai, Katsuaki, Sato, Jumpei, Utsumi, Tetsuaki, Yoneya, Kazuhide, Suematsu, Yasuhiro, Hashimoto, Toshifumi, Hioka, Takeshi, Yanagidaira, Kosuke, Kojima, Masatsugu, Matsuno, Junya, Shiraishi, Kei, Yamamoto, Kensuke, Hayashi, Shintaro, Hashiguchi, Tomoharu, Inuzuka, Kazuko, Sugahara, Akio, Honma, Mitsuaki, Tsunoda, Keiji, Yamamoto, Kazumasa, Sugimoto, Takahiro, Fujimura, Tomofumi, Kaneko, Mizuki, Date, Hiroki, Kobayashi, Osamu, Minamoto, Takatoshi, Tachibana, Ryoichi, Yamaguchi, Itaru, Lee, Juan, Ramachandra, Venky, Rajendra, Srinivas, Tang, Tianyu, Darne, Siddhesh, Lee, Jiwang, Li, Jason, Miwa, Toru, Yamashita, Ryuji, Sugawara, Hiroshi, Ookuma, Naoki, Kano, Masahiro, Mizukoshi, Hiroyuki, Kuniyoshi, Yuki, Watanabe, Mitsuyuki, Akiyama, Kei, Mori, Hirotoshi, Arimizu, Akira, Katano, Yoshito, Ehama, Masakazu, Maejima, Hiroshi, Hosono, Koji, Yoshihara, Masahiro
Published in 2021 IEEE International Solid- State Circuits Conference (ISSCC) (13.02.2021)
Published in 2021 IEEE International Solid- State Circuits Conference (ISSCC) (13.02.2021)
Get full text
Conference Proceeding
A 1-Tb 4b/Cell 4-Plane 162-Layer 3D Flash Memory With a 2.4-Gb/s I/O Speed Interface
Yuh, Jong, Li, Jason, Li, Heguang, Oyama, Yoshihiro, Hsu, Cynthia, Anantula, Pradeep, Jeong, Stanley, Amarnath, Anirudh, Darne, Siddhesh, Bhatia, Sneha, Tang, Tianyu, Arya, Aditya, Rastogi, Naman, Ookuma, Naoki, Mizukoshi, Hiroyuki, Yap, Alex, Wang, Demin, Kim, Steve, Wu, Yonggang, Peng, Min, Lu, Jason, Ip, Tommy, Malhotra, Seema, Han, David, Okumura, Masatoshi, Liu, Jiwen, Sohn, John, Chibvongodze, Hardwell, Balaga, Muralikrishna, Matsuda, Aki, Puri, Chakshu, Chen, Chen, V, Indra K, G, Chaitanya, Ramachandra, Venky, Kato, Yosuke, Kumar, Ravi, Wang, Huijuan, Moogat, Farookh, Yoon, In-Soo, Kanda, Kazushige, Shimizu, Takahiro, Shibata, Noboru, Shigeoka, Takashi, Yanagidaira, Kosuke, Kodama, Takuyo, Fukuda, Ryo, Hirashima, Yasuhiro, Abe, Mitsuhiro
Published in 2022 IEEE International Solid- State Circuits Conference (ISSCC) (20.02.2022)
Published in 2022 IEEE International Solid- State Circuits Conference (ISSCC) (20.02.2022)
Get full text
Conference Proceeding
A 19 nm 112.8 mm ^ 64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface
Kanda, K., Shibata, N., Hisada, T., Isobe, K., Sato, M., Shimizu, Y., Shimizu, T., Sugimoto, T., Kobayashi, T., Kanagawa, N., Kajitani, Y., Ogawa, T., Iwasa, K., Kojima, M., Suzuki, T., Suzuki, Y., Sakai, S., Fujimura, T., Utsunomiya, Y., Hashimoto, T., Kobayashi, N., Matsumoto, Y., Inoue, S., Honda, Y., Kato, Y., Zaitsu, S., Chibvongodze, H., Watanabe, M., Ding, H., Ookuma, N., Yamashita, R.
Published in IEEE journal of solid-state circuits (01.01.2013)
Published in IEEE journal of solid-state circuits (01.01.2013)
Get full text
Journal Article
A 19 nm 112.8 mm 2 64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface
Kanda, Kazushige, Shibata, Noboru, Hisada, Toshiki, Isobe, Katsuaki, Sato, Manabu, Shimizu, Yui, Shimizu, Takahiro, Sugimoto, Takahiro, Kobayashi, Tomohiro, Kanagawa, Naoaki, Kajitani, Yasuyuki, Ogawa, Takeshi, Iwasa, Kiyoaki, Kojima, Masatsugu, Suzuki, Toshihiro, Suzuki, Yuya, Sakai, Shintaro, Fujimura, Tomofumi, Utsunomiya, Yuko, Hashimoto, Toshifumi, Kobayashi, Naoki, Matsumoto, Yuuki, Inoue, Satoshi, Suzuki, Yoshinao, Honda, Yasuhiko, Kato, Yosuke, Zaitsu, Shingo, Chibvongodze, Hardwell, Watanabe, Mitsuyuki, Ding, Hong, Ookuma, Naoki, Yamashita, Ryuji
Published in IEEE journal of solid-state circuits (01.01.2013)
Published in IEEE journal of solid-state circuits (01.01.2013)
Get full text
Journal Article
11.1 A 512Gb 3b/cell flash memory on 64-word-line-layer BiCS technology
Yamashita, Ryuji, Magia, Sagar, Higuchi, Tsutomu, Yoneya, Kazuhide, Yamamura, Toshio, Mizukoshi, Hiroyuki, Zaitsu, Shingo, Yamashita, Minoru, Toyama, Shunichi, Kamae, Norihiro, Lee, Juan, Shuo Chen, Jiawei Tao, Mak, William, Xiaohua Zhang, Ying Yu, Utsunomiya, Yuko, Kato, Yosuke, Sakai, Manabu, Matsumoto, Masahide, Chibvongodze, Hardwell, Ookuma, Naoki, Yabe, Hiroki, Taigor, Subodh, Samineni, Rangarao, Kodama, Takuyo, Kamata, Yoshihiko, Namai, Yuzuru, Huynh, Jonathan, Sung-En Wang, Yankang He, Trung Pham, Saraf, Vivek, Petkar, Akshay, Watanabe, Mitsuyuki, Hayashi, Koichiro, Swarnkar, Prashant, Miwa, Hitoshi, Pradhan, Aditya, Dey, Sulagna, Dwibedy, Debasish, Xavier, Thushara, Balaga, Muralikrishna, Agarwal, Samiksha, Kulkarni, Swaroop, Papasaheb, Zameer, Deora, Sahil, Hong, Patrick, Meiling Wei, Balakrishnan, Gopinath, Ariki, Takuya, Verma, Kapil, Chang Siau, Yingda Dong, Ching-Huang Lu, Miwa, Toru, Moogat, Farookh
Published in 2017 IEEE International Solid-State Circuits Conference (ISSCC) (01.02.2017)
Published in 2017 IEEE International Solid-State Circuits Conference (ISSCC) (01.02.2017)
Get full text
Conference Proceeding
METHOD OF REGENERATING ORGANIC WASTE WATER AND APPARATUS THEREFOR
OOKUMA, NAOKI, YOSHIKAWA, SHINICHI, OONISHI, MAKOTO, TAKEMURA, KIYOKAZU
Year of Publication 23.10.2008
Get full text
Year of Publication 23.10.2008
Patent
Word line architecture for three dimensional NAND flash memory
Ariki, Takuya, Miwa, Toru, Ookuma, Naoki, Hayashi, Koichiro, Yabe, Hiroki
Year of Publication 16.11.2021
Get full text
Year of Publication 16.11.2021
Patent
A 19 nm 112.8 mm2 64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface
KANDA, Kazushige, SHIBATA, Noboru, KAJITANI, Yasuyuki, OGAWA, Takeshi, IWASA, Kiyoaki, KOJIMA, Masatsugu, SUZUKI, Toshihiro, SUZUKI, Yuya, SAKAI, Shintaro, FUJIMURA, Tomofumi, UTSUNOMIYA, Yuko, HASHIMOTO, Toshifumi, HISADA, Toshiki, KOBAYASHI, Naoki, MATSUMOTO, Yuuki, INOUE, Satoshi, SUZUKI, Yoshinao, HONDA, Yasuhiko, KATO, Yosuke, ZAITSU, Shingo, CHIBVONGODZE, Hardwell, WATANABE, Mitsuyuki, HONG DING, ISOBE, Katsuaki, OOKUMA, Naoki, YAMASHITA, Ryuji, SATO, Manabu, SHIMIZU, Yui, SHIMIZU, Takahiro, SUGIMOTO, Takahiro, KOBAYASHI, Tomohiro, KANAGAWA, Naoaki
Published in IEEE journal of solid-state circuits (2013)
Get full text
Published in IEEE journal of solid-state circuits (2013)
Conference Proceeding
DIFFERENTIAL DBUS SCHEME FOR LOW-LATENCY RANDOM READ FOR NAND MEMORIES
ARIKI, Takuya, OOKUMA, Naoki, MIWA, Toru, YABE, Hiroki, HAYASHI, Koichiro
Year of Publication 20.05.2021
Get full text
Year of Publication 20.05.2021
Patent
DIFFERENTIAL DBUS SCHEME FOR LOW-LATENCY RANDOM READ FOR NAND MEMORIES
Ariki, Takuya, Miwa, Toru, Ookuma, Naoki, Hayashi, Koichiro, Yabe, Hiroki
Year of Publication 13.05.2021
Get full text
Year of Publication 13.05.2021
Patent
WORD LINE ARCHITECTURE FOR THREE DIMENSIONAL NAND FLASH MEMORY
Ariki, Takuya, Miwa, Toru, Ookuma, Naoki, Hayashi, Koichiro, Yabe, Hiroki
Year of Publication 06.05.2021
Get full text
Year of Publication 06.05.2021
Patent
Differential dbus scheme for low-latency random read for NAND memories
Ariki, Takuya, Miwa, Toru, Ookuma, Naoki, Hayashi, Koichiro, Yabe, Hiroki
Year of Publication 20.04.2021
Get full text
Year of Publication 20.04.2021
Patent
Three-dimensional memory device containing bit line switches
Ariki, Takuya, Miwa, Toru, Chibvongodze, Hardwell, Nishikawa, Masatoshi, Ookuma, Naoki
Year of Publication 01.12.2020
Get full text
Year of Publication 01.12.2020
Patent