Search Results - "ONUFRYK, Peter" :: K.UTB vyhledávací portál

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UCIe: Standard for an Open Chiplet Ecosystem

by Onufryk, Peter, Choudhary, Swadesh
Published in IEEE MICRO (05.09.2024)

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Journal Article

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Network Processor Design: Issues and Practices

by Franklin, Mark A, Crowley, Patrick, Hadimioglu, Haldun, Onufryk, Peter Z
Year of Publication 2005

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eBook

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Architectural considerations for CPU and network interface integration

by Cranor, C.D., Gopalakrishnan, R., Onufryk, P.Z.
Published in IEEE MICRO (01.01.2000)

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Journal Article

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TECHNOLOGIES FOR A UNIFIED TEST AND DEBUG ARCHITECTURE

by Onufryk, Peter, Muthrasanallur, Sridhar, Choudhary, Swadesh, Pasdast, Gerald, Das Sharma, Debendra
Year of Publication 03.10.2024

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Patent

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TECHNOLOGIES FOR A UNIFIED TEST AND DEBUG ARCHITECTURE

by MUTHRASANALLUR, Sridhar, ONUFRYK, Peter, PASDAST, Gerald, DAS SHARMA, Debendra, CHOUDHARY, Swadesh
Year of Publication 03.10.2024

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Patent

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DYNAMIC SWITCHING OF DATA TRANSFERS BETWEEN SIDEBAND AND MAINBAND

by Carrieri, Enrico David, Onufryk, Peter, Nelson, Aruni P, Kuehnis, Rolf, Muthrasanallur, Sridhar
Year of Publication 04.04.2024

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Patent

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THREE DIMENSIONAL UNIVERSAL CHIPLET INTERCONNECT AS ON-PACKAGE INTERCONNECT

by Onufryk, Peter Z, Pasdast, Gerald S, Tiagaraj, Sathya Narasimman, Das Sharma, Debendra
Year of Publication 25.01.2024

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Patent

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ON-PACKAGE DIE-TO-DIE (D2D) INTERCONNECT FOR MEMORY USING UNIVERSAL CHIPLET INTERCONNECT EXPRESS (UCIE) PHY

by LANKA, Narasimha, MUTHRASANALLUR, Sridhar, ZIAKAS, Dimitrios, ONUFRYK, Peter, PASDAST, Gerald, WU, Zuoguo, DAS SHARMA, Debendra, CHOUDHARY, Swadesh
Year of Publication 26.09.2024

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Patent

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ON-ON-PACKAGE DIE-TO-DIE (D2D) INTERCONNECT FOR MEMORY USING UNIVERSAL CHIPLET INTERCONNECT EXPRESS (UCIE) PHY

by Lanka, Narasimha, Onufryk, Peter, Choudhary, Swadesh, Wu, Zuoguo, Muthrasanallur, Sridhar, Pasdast, Gerald, Ziakas, Dimitrios, Das Sharma, Debendra
Year of Publication 19.09.2024

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Patent

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Processed wafer of scalable electrical circuits, method for making same, and device comprising scaled electrical circuits

by Scatchard, Bruce, Onufryk, Peter, Xie, Chunfang
Year of Publication 10.09.2019

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Patent

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System and method with reference voltage partitioning for low density parity check decoding

by ONUFRYK PETER Z, MARELLI ALESSIA, MICHELONI RINO
Year of Publication 12.01.2016

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Patent

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System and method for generating parity data in a nonvolatile memory controller by using a distributed processing technique

by ONUFRYK PETER Z, LEVIT INNA
Year of Publication 03.12.2013

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Patent

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Method and apparatus for mapped I/O routing in an interconnect switch

by BROWN DAVID ALAN, ONUFRYK PETER Z
Year of Publication 29.09.2015

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Patent

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Method and apparatus for layer-specific LDPC decoding

by Onufryk, Peter Z, Norrie, Christopher I. W, Micheloni, Rino, Marelli, Alessia
Year of Publication 12.03.2019

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Patent

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Integrated memory for storing egressing packet data, replay data and to-be egressed data

by TSANG SIUKWIN, ONUFRYK PETER
Year of Publication 14.12.2010

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Patent

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Integrated memory for storing egressing packet data, replay data and to-be egressed data

by Tsang, Siukwin, Onufryk, Peter
Year of Publication 14.12.2010

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Patent

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PACKAGE-INTERNER DIE-ZU-DIE- (D2D-) INTERCONNECT FÜR SPEICHER UNTER VERWENDUNG VON UCIE- (UNIVERSAL CHIPLET INTERCONNECT EXPRESS) PHY

by Lanka, Narasimha, Onufryk, Peter, Choudhary, Swadesh, Wu, Zuoguo, Muthrasanallur, Sridhar, Pasdast, Gerald, Ziakas, Dimitrios, Das Sharma, Debendra
Year of Publication 19.09.2024

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Patent