PIPELINE-OPERATING TYPE MEMORY SYSTEM
SUZUKI, KUNIHIKO, AKIYAMA, NOBORU, YOKIYAMA, YUJI, OHTA, TATSUYUKI, KIBAYASHI, YUTAKA
Year of Publication 15.05.2000
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Year of Publication 15.05.2000
Patent
A 23-ns 1-Mb BiCMOS DRAM
Kitsukawa, G., Yanagisawa, K., Kobayashi, Y., Kinoshita, Y., Ohta, T., Udagawa, T., Miwa, H., Miyazawa, H., Kawajiri, Y., Ouchi, Y., Tsukada, H., Matsumoto, T., Itoh, K.
Published in IEEE journal of solid-state circuits (01.10.1990)
Published in IEEE journal of solid-state circuits (01.10.1990)
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Journal Article
Differential amplifier with a latching function and a memory apparatus employing same
KOBAYASHI; YUTAKA, AKIOKA; TAKASHI, KATSURA; KOYO, AKIYAMA; NOBORU, OHTA; TATSUYUKI
Year of Publication 13.12.1994
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Year of Publication 13.12.1994
Patent
A 23ns 1Mbit BiCMOS DRAM
Yanagisawa, Kazumasa, Kitsukawa, Goro, Kobayashi, Yutaka, Kinoshita, Yoshitaka, Ohta, Tatsuyuki, Udagawa, Tetsu, Ishii, Kyoko, Miwa, Hitoshi, Miyazawa, Hiroyuki, Ouchi, Yoshiaki, Tsukada, Hiromi, Matsumoto, Tetsuro, Itoh, Kiyoo
Published in ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference (01.09.1989)
Published in ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference (01.09.1989)
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Conference Proceeding
Dynamic Random Access Type Semiconductor Device
KOBAYASHI; YUTAKA, NOZOE; ATSUSHI, KINOSHITA; YOSHITAKA, TSUKADA; HIROMI, YANAGISAWA; KAZUMASA, NAKAMURA; MASAYUKI, OUCHI; YOSHIAKI, MIHASHI; KAZUO, ISHII; KYOKO, MATSUMOTO; TETSUROU, WADA; SHOJI, UDAGAWA; TETSU, OHTA; TATSUYUKI, MIWA; HITOSHI, KITSUKAWA; GORO
Year of Publication 09.04.1996
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Year of Publication 09.04.1996
Patent
Testing method for a semiconductor memory device
KOBAYASHI; YUTAKA, NOZOE; ATSUSHI, KINOSHITA; YOSHITAKA, TSUKADA; HIROMI, YANAGISAWA; KAZUMASA, NAKAMURA; MASAYUKI, OUCHI; YOSHIAKI, MIHASHI; KAZUO, ISHII; KYOKO, MATSUMOTO; TETSUROU, WADA; SHOJI, UDAGAWA; TETSU, OHTA; TATSUYUKI, MIWA; HITOSHI, KITSUKAWA; GORO
Year of Publication 04.01.1994
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Year of Publication 04.01.1994
Patent
Bi-CMOS semiconductor memory device, including improved layout structure and testing method
KOBAYASHI; YUTAKA, NOZOE; ATSUSHI, KINOSHITA; YOSHITAKA, TSUKADA; HIROMI, YANAGISAWA; KAZUMASA, NAKAMURA; MASAYUKI, OUCHI; YOSHIAKI, MIHASHI; KAZUO, ISHII; KYOKO, MATSUMOTO; TETSUROU, WADA; SHOJI, UDAGAWA; TETSU, OHTA; TATSUYUKI, MIWA; HITOSHI, KITSUKAWA; GORO
Year of Publication 22.09.1992
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Year of Publication 22.09.1992
Patent