Search Results - "OH, BYOUNGCHAN" :: K.UTB vyhledávací portál

Characterization of Border Trap Density With the Multifrequency Charge Pumping Technique in Dual-Layer Gate Oxide

by YOUNGHWAN SON, PARK, Sunyoung, KANG, Taewook, OH, Byoungchan, SHIN, Hyungcheol
Published in IEEE transactions on electron devices (01.08.2011)

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Characterization of an Oxide Trap Leading to Random Telegraph Noise in Gate-Induced Drain Leakage Current of DRAM Cell Transistors

by OH, Byoungchan, CHO, Heung-Jae, KIM, Heesang, SON, Younghwan, KANG, Taewook, PARK, Sunyoung, JANG, Seunghyun, LEE, Jong-Ho, SHIN, Hyungcheol
Published in IEEE transactions on electron devices (01.06.2011)

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Characterization of the Variable Retention Time in Dynamic Random Access Memory

by KIM, Heesang, OH, Byoungchan, SON, Younghwan, KIM, Kyungdo, CHA, Seon-Yong, JEONG, Jae-Goan, HONG, Sung-Joo, SHIN, Hyungcheol
Published in IEEE transactions on electron devices (01.09.2011)

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Investigation of Gate Etch Damage at Metal/High- k Gate Dielectric Stack Through Random Telegraph Noise in Gate Edge Direct Tunneling Current

by Cho, Heung-Jae, Son, Younghwan, Oh, Byoungchan, Jang, Seunghyun, Lee, Jong-Ho, Park, Byung-Gook, Shin, Hyungcheol
Published in IEEE electron device letters (01.04.2011)

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Study of Trap Models Related to the Variable Retention Time Phenomenon in DRAM

by KIM, Heesang, OH, Byoungchan, SON, Younghwan, KIM, Kyungdo, CHA, Seon-Yong, JEONG, Jae-Goan, HONG, Sung-Joo, SHIN, Hyungcheol
Published in IEEE transactions on electron devices (01.06.2011)

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Observation of Slow Oxide Traps at MOSFETs Having Metal/High-k Gate Dielectric Stack in Accumulation Mode

by CHO, Heung-Jae, SON, Younghwan, OH, Byoungchan, LEE, Sanghoon, LEE, Jong-Ho, PARK, Byung-Gook, SHIN, Hyungcheol
Published in IEEE transactions on electron devices (01.10.2010)

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f Improvement by Controlling Extrinsic Parasitics in Circuit-Level MOS Transistor

by Hee-Sauk Jhon, Jae-Hong Lee, Jaeho Lee, Byoungchan Oh, Ickhyun Song, Yeonam Yun, Byung-Gook Park, Jong-Duk Lee, Hyungcheol Shin
Published in IEEE electron device letters (01.12.2009)

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Random Telegraph Signal-Like Fluctuation Created by Fowler--Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor

by Kim, Heesang, Oh, Byoungchan, Kim, Kyungdo, Cha, Seon-Yong, Jeong, Jae-Goan, Hong, Sung-Joo, Lee, Jong-Ho, Park, Byung-Gook, Shin, Hyungcheol
Published in Japanese Journal of Applied Physics (01.09.2010)

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Rethinking DRAM's Page Mode With STT-MRAM

by Oh, Byoungchan, Abeyratne, Nilmini, Kim, Nam Sung, Ahn, Jeongseob, Dreslinski, Ronald G., Mudge, Trevor
Published in IEEE transactions on computers (01.05.2023)

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Approximations to field-effect factor and their use in GIDL modeling

by Kozhukhov, Nikita, Byoungchan Oh, Hyungcheol Shin
Published in 18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) (01.07.2011)

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Conference Proceeding

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Characterization of oxide traps by RTN measurement in MOSFETs and memory devices

by Shin, H, Byoungchan Oh
Published in 2010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (01.07.2010)

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Observation of three-level random telegraph noise in GIDL current of Saddle-Fin type DRAM cell transistor

by Byoungchan Oh, Heung-Jae Cho, Heesang Kim, Hyungcheol Shin
Published in 2010 IEEE International Memory Workshop (01.05.2010)

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Conference Proceeding

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Investigation of Gate Etch Damage at Metal/High-[Formula Omitted] Gate Dielectric Stack Through Random Telegraph Noise in Gate Edge Direct Tunneling Current

by Cho, Heung-Jae, Son, Younghwan, Oh, Byoungchan, Jang, Seunghyun, Lee, Jong-Ho, Park, Byung-Gook, Shin, Hyungcheol
Published in IEEE electron device letters (01.04.2011)

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fmax Improvement by Controlling Extrinsic Parasitics in Circuit-Level MOS Transistor

by JHON, Hee-Sauk, LEE, Jae-Hong, LEE, Jaeho, OH, Byoungchan, SONG, Ickhyun, YEONAM YUN, PARK, Byung-Gook, LEE, Jong-Duk, SHIN, Hyungcheol
Published in IEEE electron device letters (01.12.2009)

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Techniques to implement a hybrid error correction code scheme

by Wu, Wei, Oh, Byoungchan
Year of Publication 26.10.2021

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Patent

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[Formula Omitted] Improvement by Controlling Extrinsic Parasitics in Circuit-Level MOS Transistor

by Jhon, Hee-Sauk, Lee, Jae-Hong, Lee, Jaeho, Oh, Byoungchan, Song, Ickhyun, Yun, Yeonam, Park, Byung-Gook, Lee, Jong-Duk, Shin, Hyungcheol
Published in IEEE electron device letters (01.12.2009)

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Multigate MOSFET in a Bulk Technology by Integrating Polysilicon-Filled Trenches

by Ramadout, B., Guo-Neng Lu, Carrere, J.-P., Pinzelli, L., Perrot, C., Rivoire, M., Nemouchi, F.
Published in IEEE electron device letters (01.12.2009)

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f max Improvement by Controlling Extrinsic Parasitics in Circuit-Level MOS Transistor

by Jhon, Hee-Sauk, Lee, Jae-Hong, Lee, Jaeho, Oh, Byoungchan, Song, Ickhyun, Yun, Yeonam, Park, Byung-Gook, Lee, Jong-Duk, Shin, Hyungcheol
Published in IEEE electron device letters (01.01.2009)

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