A 20-nm physical gate length NMOSFET featuring 1.2 nm gate oxide, shallow implanted source and drain and BF2 pockets
Deleonibus, S., Caillat, C., Guegan, G., Heitzmann, M., Nier, M.E., Tedesco, S., Dal'zotto, B., Martin, F., Mur, P., Papon, A.M., Lecarval, G., Biswas, S., Souil, D.
Published in IEEE electron device letters (01.04.2000)
Published in IEEE electron device letters (01.04.2000)
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Journal Article
Full CMP integration of CVD TiN damascene sub-0.1-[mu]m metal gate devices for ULSI applications
Ducroquet, F, Achard, H, Coudert, F, Previtali, B, Lugand, J.-F, Ulmer, L, Farjot, T, Gobil, Y, Heitzmann, M, Tedesco, S, Nier, M.E, Deleonibus, S
Published in IEEE transactions on electron devices (01.08.2001)
Published in IEEE transactions on electron devices (01.08.2001)
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Journal Article
Full CMP integration of CVD TiN damascene sub-0.1-/spl mu/m metal gate devices for ULSI applications
Ducroquet, F., Achard, H., Coudert, F., Previtali, B., Lugand, J.-F., Ulmer, L., Farjot, T., Gobil, Y., Heitzmann, M., Tedesco, S., Nier, M.E., Deleonibus, S.
Published in IEEE transactions on electron devices (01.08.2001)
Published in IEEE transactions on electron devices (01.08.2001)
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Journal Article
Realization of two-dimensional optical devices using photonic band gap structures on silicon-on-insulator
Charvolin, T., Hadji, E., Picard, E., Zelsman, M., Assous, M., Dalzotto, B., Nier, M.E., Tedesco, S., Letartre, X., Rojo-Roméo, P., Seassal, C.
Published in Microelectronic engineering (01.07.2002)
Published in Microelectronic engineering (01.07.2002)
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Journal Article
Conference Proceeding
Poly-Si gate patterning issues for ultimate MOSFET
Louis, D., Nier, M.E., Fery, C., Heitzmann, M., Papon, A.M., Renard, S.
Published in Microelectronic engineering (01.07.2002)
Published in Microelectronic engineering (01.07.2002)
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Journal Article
Conference Proceeding
Full CMP integration of CVD TiN damascene sub-0.1-μm metal gate devices for ULSI applications
Ducroquet, F., Achard, H., Coudert, F., Previtali, B., Lugand, J.-F., Ulmer, L., Farjot, T., Gobil, Y., Heitzmann, M., Tedesco, S., Nier, M.E., Deleonibus, S.
Published in IEEE transactions on electron devices (01.08.2001)
Published in IEEE transactions on electron devices (01.08.2001)
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Journal Article
Process development for 30 nm poly gate patterning on 1.2 nm oxide
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Journal Article
Conference Proceeding
A 20-nm physical gate length NMOSFET featuring 1.2 nm gate oxide, shallow implanted source and drain and BF 2 pockets
Deleonibus, S., Caillat, C., Guegan, G., Heitzmann, M., Nier, M.E., Tedesco, S., Dal'zotto, B., Martin, F., Mur, P., Papon, A.M., Lecarval, G., Biswas, S., Souil, D.
Published in IEEE electron device letters (01.04.2000)
Published in IEEE electron device letters (01.04.2000)
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Journal Article
A 0.10 μm buried p-channel MOSFET with through the gate boron implantation and arsenic tilted pocket
Guegan, G., Deleonibus, S., Caillat, C., Tedesco, S., Dal’zotto, B., Heitzmann, M., Nier, M.E., Mur, P.
Published in Solid-state electronics (01.03.2002)
Published in Solid-state electronics (01.03.2002)
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Journal Article
A 20 nm physical gate length NMOSFET with a 1.2 nm gate oxide fabricated by mixed dry and wet hard mask etching
Caillat, C., Deleonibus, S., Guegan, G., Heitzmann, M., Nier, M.E., Tedesco, S., Dal'zotto, B., Martin, F., Mur, P., Papon, A.M., Lecarval, G., Previtali, B., Toffoli, A., Allain, F., Biswas, S., Jourdan, F., Fugier, P., Dichiaro, J.L.
Published in Solid-state electronics (01.03.2002)
Published in Solid-state electronics (01.03.2002)
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Journal Article
Fabrication of Single Electron Devices by hybrid (E-beam/DUV) lithography
Palun, L., Tedesco, S., Heitzman, M., Martin, F., Fraboulet, D., Dal'zotto, B., Nier, M.E., Mur, P., Charvolin, T., Mariolle, D., Tardif, F.
Published in Microelectronic engineering (01.06.2000)
Published in Microelectronic engineering (01.06.2000)
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Journal Article
Conference Proceeding
Gate and Source/Drain Engineering for 50 nm P-Channel MOSFET
Guegan, G., Deleonibus, S., Bertrand, G., Souil, D., Rivallin, P., Tedesco, S., Mur, P., Holliger, P., Nier, M.E.
Published in 31st European Solid-State Device Research Conference (2001)
Published in 31st European Solid-State Device Research Conference (2001)
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Conference Proceeding
Coulomb Blockade in Thin SOI Nanodevices
Fraboulet, D., Jehl, X., Mariolle, D., Le Royer, C., Le Carval, G., Scheiblin, P., Rivallin, P., Mollard, L., Deleroyelle, D., Nier, M.E., Toffoli, A., Molas, G., De Salvo, B., Deleonibus, S., Sanquer, M.
Published in 32nd European Solid-State Device Research Conference (2002)
Published in 32nd European Solid-State Device Research Conference (2002)
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Conference Proceeding
Full CMP Integration of TiN Damascene Metal Gate Devices
Achard, H., Ducroquet, F., Coudert, F., Previtali, B., Lugand, J.F., Ulmer, L., Farjot, T., Gobil, Y., Heitzmann, M., Tedesco, S., Nier, M.E., Deleonibus, S.
Published in 30th European Solid-State Device Research Conference (2000)
Published in 30th European Solid-State Device Research Conference (2000)
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Conference Proceeding
Channel Engineering Study for 50 nm P-Channel MOSFET
Guegan, G., Souil, D., Deleonibus, S., Tedesco, S., Laviron, C., Previtali, P., Nier, M.E.
Published in 32nd European Solid-State Device Research Conference (2002)
Published in 32nd European Solid-State Device Research Conference (2002)
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Conference Proceeding