Search Results - "Nallapati Giridhar" :: K.UTB vyhledávací portál

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감소된 커플링 저항을 위해 수직으로 인접한 인터커넥트 층들 사이에 직접 커플링되는 금속 라인들을 이용하는 집적 회로(IC)들 및 관련 방법들

by ZHU JOHN JIANHONG, BAO JUNJING, NALLAPATI GIRIDHAR
Year of Publication 30.04.2024

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시스템 온 칩(SOC) 상의 다수의 기능 블록

by ZHU JOHN JIANHONG, BAO JUNJING, NALLAPATI GIRIDHAR
Year of Publication 27.12.2023

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최상부 접점을 갖는 금속-절연체-금속 커패시터

by ZHU JOHN JIANHONG, GE LIXIN, NALLAPATI GIRIDHAR
Year of Publication 24.04.2024

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집적 회로 다이의 상호연결 층 상의 층간 매체 내 딥 트렌치 커패시터들 및 관련 방법들

by CHOI JIHONG, CHIDAMBARAM PERIANNAN, NALLAPATI GIRIDHAR, SONG STANLEY SEUNGCHUL
Year of Publication 19.01.2024

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집적 회로(IC) 칩을 패키지 기판에 인터페이싱하기 위한 커패시터 내장형 재배선 층(RDL) 기판을 채용하는 IC 패키지들 및 관련 방법들

by CHOI JIHONG, KIM JONGHAE, STONE WILLIAM, CHIDAMBARAM PERIANNAN, SYED AHMER, NALLAPATI GIRIDHAR, XU JIANWEN
Year of Publication 02.01.2024

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LOCAL INTERCONNECT STRUCTURES FOR HIGH DENSITY

by CHIDAMBARAM PR, ZHU JOHN JIANHONG, NALLAPATI GIRIDHAR
Year of Publication 23.10.2015

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SHARED-DIFFUSION STANDARD CELL ARCHITECTURE

by VANG FOUA, KAMAL PRATYUSH, TERZIOGLU ESIN, PATEL PRAYAG BHANUBHAI, DATTA ANIMESH, NALLAPATI GIRIDHAR
Year of Publication 16.06.2015

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INTEGRATED CIRCUITS (ICS) EMPLOYING DIRECTLY COUPLED METAL LINES BETWEEN VERTICALLY-ADJACENT INTERCONNECT LAYERS FOR REDUCED COUPLING RESISTANCE, AND RELATED METHODS

by NALLAPATI, Giridhar, BAO, Junjing, ZHU, John Jianhong
Year of Publication 24.07.2024

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INTEGRATED CIRCUITS (ICs) EMPLOYING DIRECTLY COUPLED METAL LINES BETWEEN VERTICALLY-ADJACENT INTERCONNECT LAYERS FOR REDUCED COUPLING RESISTANCE, AND RELATED METHODS

by Zhu, John Jianhong, Nallapati, Giridhar, Bao, Junjing
Year of Publication 20.06.2024

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Metal-insulator-metal capacitor with top contact

by Zhu, John Jianhong, Nallapati, Giridhar, Ge, Lixin
Year of Publication 30.04.2024

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Integrated circuits (ICs) employing directly coupled metal lines between vertically-adjacent interconnect layers for reduced coupling resistance, and related methods

by Zhu, John Jianhong, Nallapati, Giridhar, Bao, Junjing
Year of Publication 26.03.2024

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VERTICAL CHANNEL FIELD EFFECT TRANSISTOR (VCFET) WITH REDUCED CONTACT RESISTANCE AND/OR PARASITIC CAPACITANCE, AND RELATED FABRICATION METHODS

by Li, Xia, Nallapati, Giridhar, Bao, Junjing
Year of Publication 21.03.2024

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MULTIPLE FUNCTION BLOCKS ON A SYSTEM ON A CHIP (SOC)

by NALLAPATI, Giridhar, BAO, Junjing, ZHU, John Jianhong
Year of Publication 28.02.2024

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TRANSISTOR CELL WITH SELF-ALIGNED GATE CONTACT

by NALLAPATI, Giridhar, BAO, Junjing, ZHU, John Jianhong
Year of Publication 28.02.2024

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LOW VIA RESISTANCE INTERCONNECT STRUCTURE

by NALLAPATI, Giridhar, BAO, Junjing, ZHU, John
Year of Publication 20.07.2023

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LOW VIA RESISTANCE INTERCONNECT STRUCTURE

by Zhu, John Jianhong, Nallapati, Giridhar, BAO, Junjing
Year of Publication 13.07.2023

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INTEGRATED CIRCUITS (ICs) EMPLOYING DIRECTLY COUPLED METAL LINES BETWEEN VERTICALLY-ADJACENT INTERCONNECT LAYERS FOR REDUCED COUPLING RESISTANCE, AND RELATED METHODS

by Zhu, John Jianhong, Nallapati, Giridhar, Bao, Junjing
Year of Publication 06.04.2023

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INTEGRATED CIRCUITS (ICs) EMPLOYING DIRECTLY COUPLED METAL LINES BETWEEN VERTICALLY-ADJACENT INTERCONNECT LAYERS FOR REDUCED COUPLING RESISTANCE, AND RELATED METHODS

by NALLAPATI, Giridhar, BAO, Junjing, ZHU, John Jianhong
Year of Publication 23.03.2023

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METAL-INSULATOR-METAL CAPACITOR WITH TOP CONTACT

by NALLAPATI, Giridhar, ZHU, John Jianhong, GE, Lixin
Year of Publication 17.07.2024

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COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) WITH BALANCED N AND P DRIVE CURRENT

by NALLAPATI, Giridhar, BAO, Junjing, LI, Xia
Year of Publication 27.06.2024

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