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"Nallapati Giridhar"
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"Nallapati Giridhar"
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TRANSISTOR CELL WITH SELF-ALIGNED GATE CONTACT
by
NALLAPATI
,
Giridhar
,
BAO, Junjing
,
ZHU, John Jianhong
Year of Publication
27.10.2022
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MULTIPLE FUNCTION BLOCKS ON A SYSTEM ON A CHIP (SOC)
by
NALLAPATI
,
Giridhar
,
BAO, Junjing
,
ZHU, John Jianhong
Year of Publication
27.10.2022
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COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) WITH BALANCED N AND P DRIVE CURRENT
by
NALLAPATI
,
Giridhar
,
BAO, Junjing
,
LI, Xia
Year of Publication
20.06.2024
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MULTIPLE FUNCTION BLOCKS ON A SYSTEM ON A CHIP (SOC)
by
NALLAPATI
,
Giridhar
,
BAO, Junjing
,
ZHU, John Jianhong
Year of Publication
20.10.2022
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TRANSISTOR CELL WITH SELF-ALIGNED GATE CONTACT
by
NALLAPATI
,
Giridhar
,
BAO, Junjing
,
ZHU, John Jianhong
Year of Publication
20.10.2022
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HYBRID LOW RESISTANCE METAL LINES
by
NALLAPATI
,
Giridhar
,
BAO, Junjing
,
ZHU, John Jianhong
Year of Publication
12.10.2022
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VERTICAL CHANNEL FIELD EFFECT TRANSISTOR (VCFET) WITH REDUCED CONTACT RESISTANCE AND/OR PARASITIC CAPACITANCE, AND RELATED FABRICATION METHODS
by
NALLAPATI
,
Giridhar
,
BAO, Junjing
,
LI, Xia
Year of Publication
16.05.2024
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Deep trench capacitors in an inter-layer medium on an interconnect layer of an integrated circuit die and related methods
by
Choi, Jihong
,
Nallapati
,
Giridhar
,
Song, Stanley Seungchul
,
Chidambaram, Periannan
Year of Publication
30.04.2024
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Hybrid low resistance metal lines
by
Zhu, John Jianhong
,
Nallapati
,
Giridhar
,
Bao, Junjing
Year of Publication
02.08.2022
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VERTICAL CHANNEL FIELD EFFECT TRANSISTOR (VCFET) WITH REDUCED CONTACT RESISTANCE AND/OR PARASITIC CAPACITANCE, AND RELATED FABRICATION METHODS
by
NALLAPATI
,
Giridhar
,
BAO, Junjing
,
LI, Xia
Year of Publication
28.03.2024
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DEEP TRENCH CAPACITORS IN AN INTER-LAYER MEDIUM ON AN INTERCONNECT LAYER OF AN INTEGRATED CIRCUIT DIE AND RELATED METHODS
by
NALLAPATI
,
Giridhar
,
SONG, Stanley Seungchul
,
CHIDAMBARAM, Periannan
,
CHOI, Jihong
Year of Publication
27.03.2024
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INTEGRATED CIRCUIT (IC) PACKAGES EMPLOYING CAPACITOR INTERPOSER SUBSTRATE WITH ALIGNED EXTERNAL INTERCONNECTS, AND RELATED FABRICATION METHODS
by
Choi, Jihong
,
He, Dongming
,
Nallapati
,
Giridhar
,
Zhao, Lily
Year of Publication
07.03.2024
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INTEGRATED CIRCUIT (IC) PACKAGES EMPLOYING CAPACITOR INTERPOSER SUBSTRATE WITH ALIGNED EXTERNAL INTERCONNECTS, AND RELATED FABRICATION METHODS
by
NALLAPATI
,
Giridhar
,
ZHAO, Lily
,
HE, Dongming
,
CHOI, Jihong
Year of Publication
07.03.2024
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Estructuras de interconexión local para alta densidad
by
NALLAPATI
,
Giridhar
,
CHIDAMBARAM, Pr
,
ZHU, John Jianhong
Year of Publication
11.04.2022
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LOCAL INTERCONNECT STRUCTURES FOR HIGH DENSITY
by
NALLAPATI
,
Giridhar
,
CHIDAMBARAM, Pr
,
ZHU, John Jianhong
Year of Publication
15.12.2021
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A VIA ZERO INTERCONNECT LAYER METAL RESISTOR INTEGRATION
by
NALLAPATI
,
Giridhar
,
BAO, Junjing
,
FENG, Peijie
Year of Publication
07.10.2021
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VIA ZERO INTERCONNECT LAYER METAL RESISTOR INTEGRATION
by
NALLAPATI
,
Giridhar
,
BAO, Junjing
,
FENG, Peijie
Year of Publication
30.09.2021
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METAL-INSULATOR-METAL CAPACITOR WITH TOP CONTACT
by
NALLAPATI
,
Giridhar
,
ZHU, John Jianhong
,
GE, Lixin
Year of Publication
16.03.2023
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METAL-INSULATOR-METAL CAPACITOR WITH TOP CONTACT
by
NALLAPATI
,
Giridhar
,
ZHU, John Jianhong
,
GE, Lixin
Year of Publication
09.03.2023
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HYBRID LOW RESISTANCE METAL LINES
by
NALLAPATI
,
Giridhar
,
BAO, Junjing
,
ZHU, John Jianhong
Year of Publication
10.06.2021
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