Mobile CPU power/performance benchmarking and process technology co-optimization
Bucki, R., Bridges, T., Bowers, B., Xue, T., Mir, I., Le, D., Kazi, T., Fischer, J., Ekbote, S., Sengupta, S., Nallapati, G.
Published in 2014 IEEE International Conference on IC Design & Technology (01.05.2014)
Published in 2014 IEEE International Conference on IC Design & Technology (01.05.2014)
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Conference Proceeding
Cost and power/performance optimized 20nm SoC technology for advanced mobile devices
Nallapati, G., Zhu, J., Wang, J., Sheu, J. Y., Cheng, K. L., Gan, C., Yang, D., Cai, M., Cheng, J., Ge, L., Chen, Y., Bucki, R., Bowers, B., Vang, F., Chen, X., Kwon, O., Yoon, S., Wu, C. C., Chidambaram, Pr, Cao, M., Fischer, J., Terzioglu, E., Mii, Y. J., Yeap, G.
Published in 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers (01.06.2014)
Published in 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers (01.06.2014)
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Conference Proceeding
Low power embedded memory design - process to system level considerations
Terzioglu, E, Sei Seung Yoon, ChangHo Jung, Chaba, R, Boynapalli, V, Abu-Rahma, M, Wang, J, Yang, S, Nallapati, G, Thean, A, Chidambaram, C, Han, M, Yeap, G, Sani, M
Published in 2011 IEEE International Conference on IC Design & Technology (01.05.2011)
Published in 2011 IEEE International Conference on IC Design & Technology (01.05.2011)
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Conference Proceeding
Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes
Song, S. C., Xu, J., Yang, D., Rim, K., Feng, P., Bao, J., Zhu, J., Wang, J., Nallapati, G., Badaroglu, M., Narayanasetti, P., Bucki, B., Fischer, J., Yeap, Geoffrey
Published in 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) (01.06.2016)
Published in 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) (01.06.2016)
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