Pipelined Non-strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories
Khanna, Sudhanshu, Nalam, Satyanand V., Calhoun, Benton H.
Published in 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems (01.01.2014)
Published in 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems (01.01.2014)
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Conference Proceeding
Journal Article
Asymmetric sizing in a 45nm 5T SRAM to improve read stability over 6T
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Conference Proceeding
5.6 Mb/mm ^ 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology
Kulkarni, Jaydeep P., Keane, John, Kyung-Hoae Koo, Nalam, Satyanand, Zheng Guo, Karl, Eric, Zhang, Kevin
Published in IEEE journal of solid-state circuits (01.01.2017)
Published in IEEE journal of solid-state circuits (01.01.2017)
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Journal Article
A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry
Karl, Eric, Zheng Guo, Conary, James, Miller, Jeffrey, Yong-Gee Ng, Nalam, Satyanand, Daeyeon Kim, Keane, John, Xiaofei Wang, Bhattacharya, Uddalak, Zhang, Kevin
Published in IEEE journal of solid-state circuits (01.01.2016)
Published in IEEE journal of solid-state circuits (01.01.2016)
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Journal Article
Impact of circuit assist methods on margin and performance in 6T SRAM
Mann, Randy W., Wang, Jiajing, Nalam, Satyanand, Khanna, Sudhanshu, Braceras, Geordie, Pilo, Harold, Calhoun, Benton H.
Published in Solid-state electronics (01.11.2010)
Published in Solid-state electronics (01.11.2010)
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Journal Article
Sub-550mV SRAM Design in 22nm FinFET Low Power (22FFL) Technology with Self-Induced Collapse Write Assist
Kim, Daeyeon, Wiedemer, Jami, Kolar, Pramod, Shrivastava, Ayush, Shah, Jinal, Nalam, Satyanand, Baek, Gwanghyeon, Wang, Xiaofei, Guo, Zheng, Karl, Eric
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Conference Proceeding
A 23.6Mb/mm2 SRAM in 10nm FinFET technology with pulsed PMOS TVC and stepped-WL for low-voltage applications
Zheng Guo, Daeyeon Kim, Nalam, Satyanand, Wiedemer, Jami, Xiaofei Wang, Karl, Eric
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01.02.2018)
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01.02.2018)
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Conference Proceeding
17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology
Keane, John, Kulkarni, Jaydeep, Kyung-Hoae Koo, Nalam, Satyanand, Zheng Guo, Karl, Eric, Zhang, Kevin
Published in 2016 IEEE International Solid-State Circuits Conference (ISSCC) (01.01.2016)
Published in 2016 IEEE International Solid-State Circuits Conference (ISSCC) (01.01.2016)
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Conference Proceeding
Analyzing static and dynamic write margin for nanometer SRAMs
Wang, Jiajing, Nalam, Satyanand, Calhoun, Benton H.
Published in Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) (11.08.2008)
Published in Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) (11.08.2008)
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Conference Proceeding
17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology
Karl, Eric, Zheng Guo, Conary, James W., Miller, Jeffrey L., Yong-Gee Ng, Nalam, Satyanand, Daeyeon Kim, Keane, John, Bhattacharya, Uddalak, Zhang, Kevin
Published in 2015 IEEE International Solid State Circuits Conference (ISSCC) (01.02.2015)
Published in 2015 IEEE International Solid State Circuits Conference (ISSCC) (01.02.2015)
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Conference Proceeding
Journal Article
Virtual prototyper (ViPro): An early design space exploration and optimization tool for SRAM designers
Nalam, Satyanand, Bhargava, Mudit, Ken Mai, Calhoun, Benton H
Published in Design Automation Conference (01.06.2010)
Published in Design Automation Conference (01.06.2010)
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Conference Proceeding
A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes
Nalam, S., Bhargava, M., Ringgenberg, K., Ken Mai, Calhoun, B.H.
Published in 2009 IEEE International Conference on Computer Design (01.10.2009)
Published in 2009 IEEE International Conference on Computer Design (01.10.2009)
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Conference Proceeding
Improving SRAM Vmin and yield by using variation-aware BTI stress
Jiajing Wang, Nalam, S, Zhenyu Qi, Mann, R W, Stan, M, Calhoun, B H
Published in IEEE Custom Integrated Circuits Conference 2010 (01.09.2010)
Published in IEEE Custom Integrated Circuits Conference 2010 (01.09.2010)
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Conference Proceeding
Memory with improved read stability
CHANDRA VIKAS, NALAM SATYANAND VIJAY, AITKEN ROBERT CAMPBELL, PIETRZYK CEZARY
Year of Publication 29.04.2015
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Year of Publication 29.04.2015
Patent
Limits of bias based assist methods in nano-scale 6T SRAM
Mann, Randy W, Nalam, Satyanand, Jiajing Wang, Calhoun, Benton H
Published in 2010 11th International Symposium on Quality Electronic Design (ISQED) (01.03.2010)
Published in 2010 11th International Symposium on Quality Electronic Design (ISQED) (01.03.2010)
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Conference Proceeding
Memory with improved read stability
Chandra, Vikas, Nalam, Satyanand Vijay, Pietrzyk, Cezary, Aitken, Robert Campbell
Year of Publication 25.12.2012
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Year of Publication 25.12.2012
Patent
Memory with improved read stability
CHANDRA VIKAS, NALAM SATYANAND VIJAY, AITKEN ROBERT CAMPBELL, PIETRZYK CEZARY
Year of Publication 25.12.2012
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Year of Publication 25.12.2012
Patent
Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation
Nalam, Satyanand, Chandra, Vikas, Pietrzyk, Cezary, Aitken, Robert C, Calhoun, Benton H
Published in 2010 11th International Symposium on Quality Electronic Design (ISQED) (01.03.2010)
Published in 2010 11th International Symposium on Quality Electronic Design (ISQED) (01.03.2010)
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Conference Proceeding