Implementation of Analog Perceptron as an Essential Element of Configurable Neural Networks
Geng, Chao, Sun, Qingji, Nakatake, Shigetoshi
Published in Sensors (Basel, Switzerland) (29.07.2020)
Published in Sensors (Basel, Switzerland) (29.07.2020)
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Journal Article
A Fully Synthesizable, 0.3V, 10nW Rail-to-rail Dynamic Voltage Comparator
Zou, Xuncheng, Nakatake, Shigetoshi
Published in 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS) (01.08.2020)
Published in 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS) (01.08.2020)
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Conference Proceeding
Subblock-level matching layout for analog block-pair and its manufacturability evaluation
Hirata, Takuya, Nishino, Ryuta, Nakatake, Shigetoshi, Shimoyama, Masaya, Miyagawa, Masashi, Tanno, Koichi, Yamada, Akihiro
Published in 2015 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2015)
Published in 2015 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2015)
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Conference Proceeding
Structured analog circuit design and MOS transistor decomposition for high accuracy applications
Bo Yang, Qing Dong, Jing Li, Nakatake, S
Published in 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (01.11.2010)
Published in 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (01.11.2010)
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Conference Proceeding
Structured Placement with Topological Regularity Evaluation
Dong, Qing, Nakatake, Shigetoshi
Published in IPSJ Transactions on System LSI Design Methodology (2009)
Published in IPSJ Transactions on System LSI Design Methodology (2009)
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Journal Article
Analog perceptron circuit with DAC-based multiplier
Ishiguchi, Yoritaka, Isogai, Daishi, Osawa, Takuma, Nakatake, Shigetoshi
Published in Integration (Amsterdam) (01.09.2018)
Published in Integration (Amsterdam) (01.09.2018)
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Journal Article
Explicit layout pattern density controlling based on transistor-array-style
Chao Geng, Bo Liu, Nakatake, Shigetoshi
Published in 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS) (01.08.2017)
Published in 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS) (01.08.2017)
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Conference Proceeding
Transistor channel decomposition for structured analog layout, manufacturability and low-power applications
Qing Dong, Bo Yang, Gong Chen, Jing Li, Nakatake, S.
Published in Thirteenth International Symposium on Quality Electronic Design (ISQED) (01.03.2012)
Published in Thirteenth International Symposium on Quality Electronic Design (ISQED) (01.03.2012)
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Conference Proceeding
D-A converter based variation analysis for analog layout design
Bo Liu, Fujimura, T., Bo Yang, Nakatake, S.
Published in 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) (01.01.2010)
Published in 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) (01.01.2010)
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Conference Proceeding
An Impedance Measurement of Intravesical Urine Volume Appropriate to Seated Posture
Sakai, Ryosuke, Nakatake, Shigetoshi
Published in 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) (01.11.2019)
Published in 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) (01.11.2019)
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Conference Proceeding
Routability of twisted common-centroid capacitor array under signal coupling constraints
Gong Chen, Bo Liu, Nakatake, Shigetoshi, Bo Yang
Published in 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS) (01.10.2016)
Published in 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS) (01.10.2016)
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Conference Proceeding