A 0.9-V 1T1C SBT-based embedded nonvolatile FeRAM with a reference voltage scheme and multilayer shielded bit-line structure
Yamaoka, K., Iwanari, S., Murakuki, Y., Hirano, H., Sakagami, M., Nakakuma, T., Miki, T., Gohou, Y.
Published in IEEE journal of solid-state circuits (01.01.2005)
Published in IEEE journal of solid-state circuits (01.01.2005)
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REFERENCE POTENTIAL GENERATOR AND SEMICONDUCTOR MEMORY DEVICE
HIRANO, HIROSHIGE, NAKAKUMA, TETSUJI, SUMI, TATSUMI, MUKUNOKI, TOSHIO, MORIWAKI, NOBUYUKI, NAKANE, JOJI
Year of Publication 01.12.1999
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Year of Publication 01.12.1999
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SEMICONDUCTOR MEMORY DEVICE
HIRANO, HIROSHIGE, NAKAKUMA, TETSUJI, SUMI, TATSUMI, MUKUNOKI, TOSHIO, MORIWAKI, NOBUYUKI, NAKANE, JOJI
Year of Publication 15.06.1999
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Year of Publication 15.06.1999
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SEMICONDUCTOR MEMORY DEVICE WITH REDUNDANT MEMORY CELL BACKUP
HIRANO, HIROSHIGE, NAKAKUMA, TETSUJI, SUMI, TATSUMI, MORIWAKI, NOBUYUKI, NAKANE, JOJI, MOKUNOKI, TOSHIO
Year of Publication 15.06.1999
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Year of Publication 15.06.1999
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