Search Results - "NII, KOJI" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology

A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology

by Ishii, Yuichiro, Tanaka, Miki, Yabuuchi, Makoto, Sawada, Yohei, Tanaka, Shinji, Nii, Koji, Lu, Tien Yu, Huang, Chun Hsien, Chen, Shou Sian, Kuo, Yu Tse, Lung, Ching Cheng, Cheng, Osbert
Published in Japanese Journal of Applied Physics (01.04.2018)

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Journal Article

False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation

False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation

by Sawada, Takuya, Takata, Hidehiro, Nii, Koji, Nagata, Makoto
Published in Japanese Journal of Applied Physics (01.04.2013)

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Journal Article

Automotive low power technology for IoT society

Automotive low power technology for IoT society

by Yamauchi, Tadaaki, Kondo, Hiroyuki, Nii, Koji
Published in 2015 Symposium on VLSI Technology (VLSI Technology) (01.06.2015)

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Conference Proceeding Journal Article

Study of impact of BTI's local layout effect including recovery effect on various standard-cells in 10nm FinFET

Study of impact of BTI's local layout effect including recovery effect on various standard-cells in 10nm FinFET

by Igarashi, Mitsuhiko, Uchida, Yuuki, Takazawa, Yoshio, Tsukamoto, Yasumasa, Shibutani, Koji, Nii, Koji
Published in 2018 IEEE International Reliability Physics Symposium (IRPS) (01.03.2018)

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Conference Proceeding

Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing

Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing

by Yokoyama, Yoshisato, Nii, Koji, Ishii, Yuichiro, Tanaka, Shinji, Kobayashi, Kazutoshi
Published in IEEE journal of solid-state circuits (01.07.2023)

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Journal Article

Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs

Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs

by Yokoyama, Yoshisato, Ishii, Yuichiro, Nii, Koji, Kobayashi, Kazutoshi
Published in IEEE transactions on very large scale integration (VLSI) systems (01.07.2021)

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Journal Article

SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE

by NII KOJI
Year of Publication 15.03.2018

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Patent

3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM With Leakage Saving Circuits in 3-nm FinFET for HPC Applications

3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM With Leakage Saving Circuits in 3-nm FinFET for HPC Applications

by Osada, Yoshiaki, Nakazato, Takaaki, Aoyagi, Yumito, Nii, Koji, Liaw, Jhon-Jhy, Wu, Shien-Yang, Li, Quincy, Fujiwara, Hidehiro, Liao, Hung-Jen, Chang, Tsung-Yung Jonathan
Published in IEEE journal of solid-state circuits (19.08.2024)

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Journal Article

Design Choice in 45-nm Dual-Port SRAM — 8T, 10T Single End, and 10T Differential

Design Choice in 45-nm Dual-Port SRAM — 8T, 10T Single End, and 10T Differential

by Noguchi, Hiroki, Iguchi, Yusuke, Fujiwara, Hidehiro, Okumura, Shunsuke, Nii, Koji, Kawaguchi, Hiroshi, Yoshimoto, Masahiko
Published in IPSJ Transactions on System LSI Design Methodology (2011)

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Journal Article

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

by NII KOJI
Year of Publication 14.04.2016

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Patent

SEMICONDUCTOR MEMORY DEVICE

SEMICONDUCTOR MEMORY DEVICE

by NII KOJI, YABUUCHI MAKOTO
Year of Publication 01.07.2019

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Patent

A 3-nm FinFET 27.6-Mbit/mm 2 Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking

A 3-nm FinFET 27.6-Mbit/mm 2 Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking

by Aoyagi, Yumito, Nii, Koji, Yabuuchi, Makoto, Tanaka, Tomotaka, Ishii, Yuichiro, Osada, Yoshiaki, Nakazato, Takaaki, Wang, Isabel, Hsu, Yu-Hao, Cheng, Hong-Chen, Liao, Hung-Jen, Chang, Tsung-Yung Jonathan
Published in IEEE journal of solid-state circuits (01.04.2024)

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Journal Article

A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS

A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS

by Hayashi, Isamu, Amano, Teruhiko, Watanabe, Naoya, Yano, Yuji, Kuroda, Yasuto, Shirata, Masaya, Dosaka, Katsumi, Nii, Koji, Noda, Hideyuki, Kawai, Hiroyuki
Published in IEEE journal of solid-state circuits (01.11.2013)

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Journal Article Conference Proceeding

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

by NII, KOJI
Year of Publication 12.02.2015

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Patent

A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures

A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures

by Yabuuchi, Makoto, Tsukamoto, Yasumasa, Fujiwara, Hidehiro, Tanaka, Miki, Shinji, Shinji, Nii, Koji
Published in IEEE transactions on very large scale integration (VLSI) systems (01.11.2018)

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Journal Article

A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking

A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking

by Aoyagi, Yumito, Nii, Koji, Yabuuchi, Makoto, Tanaka, Tomotaka, Ishii, Yuichiro, Osada, Yoshiaki, Nakazato, Takaaki, Wang, Isabel, Hsu, Yu-Hao, Cheng, Hong-Chen, Liao, Hung-Jen, Chang, Tsung-Yung Jonathan
Published in IEEE journal of solid-state circuits (01.04.2024)

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Journal Article

A 28-nm 0.8M-weights/mm2 9.1-TOPS/mm2 SRAM-Based All-Analog Compute-In-Memory Using Fine-Grained Structured Pruning with Adaptive-Ranging ADC

A 28-nm 0.8M-weights/mm2 9.1-TOPS/mm2 SRAM-Based All-Analog Compute-In-Memory Using Fine-Grained Structured Pruning with Adaptive-Ranging ADC

by Shiba, Kota, Zhan, Zhijie, Nii, Koji, Wang, Yih, Chang, Tsung-Yung Jonathan, Kosuge, Atsutake, Hamada, Mototsugu, Kuroda, Tadahiro
Published in 2024 IEEE European Solid-State Electronics Research Conference (ESSERC) (09.09.2024)

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Conference Proceeding

An Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic Interference

An Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic Interference

by Sawada, Takuya, Yoshikawa, Kumpei, Takata, Hidehiro, Nii, Koji, Nagata, Makoto
Published in IEEE transactions on very large scale integration (VLSI) systems (01.10.2015)

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Journal Article

A 0.41 μA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS

A 0.41 μA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS

by MAEDA, Noriaki, KOMATSU, Shigenobu, MORIMOTO, Masao, TANAKA, Koji, TSUKAMOTO, Yasumasa, NII, Koji, SHIMAZAKI, Yasuhisa
Published in IEEE journal of solid-state circuits (01.04.2013)

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Conference Proceeding

An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment

An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment

by Morita, Y., Fujiwara, H., Noguchi, H., Iguchi, Y., Nii, K., Kawaguchi, H., Yoshimoto, M.
Published in 2007 IEEE Symposium on VLSI Circuits (01.06.2007)

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Conference Proceeding

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