Sub-Micron-Accuracy Gold-to-Gold Interconnection Flip-Chip Bonding Approach for Electronics--Optics Heterogeneous Integration
Tung, Bui Thanh, Suzuki, Motohiro, Kato, Fumiki, Nemoto, Shunsuke, Watanabe, Naoki, Aoyagi, Masahiro
Published in Japanese Journal of Applied Physics (01.04.2013)
Published in Japanese Journal of Applied Physics (01.04.2013)
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Journal Article
15-µm-pitch Cu/Au interconnections relied on self-aligned low-temperature thermosonic flip-chip bonding technique for advanced chip stacking applications
Tung, Bui Thanh, Kato, Fumiki, Watanabe, Naoya, Nemoto, Shunsuke, Kikuchi, Katsuya, Aoyagi, Masahiro
Published in Japanese Journal of Applied Physics (17.03.2014)
Published in Japanese Journal of Applied Physics (17.03.2014)
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Journal Article
Erratum: "Sub-Micron-Accuracy Gold-to-Gold Interconnection Flip-Chip Bonding Approach for Electronics--Optics Heterogeneous Integration"
Bui, Tung Thanh, Suzuki, Motohiro, Kato, Fumiki, Nemoto, Shunsuke, Watanabe, Naoya, Aoyagi, Masahiro
Published in Japanese Journal of Applied Physics (25.06.2013)
Published in Japanese Journal of Applied Physics (25.06.2013)
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Journal Article
Development of micro bump joints fabrication process using cone shape Au bumps for 3D LSI chip stacking
Imura, Fumito, Watanabe, Naoya, Nemoto, Shunsuke, Wei Feng, Kikuchi, Katsuya, Nakagawa, Hiroshi, Aoyagi, Masashiro
Published in 2014 IEEE 64th Electronic Components and Technology Conference (ECTC) (01.05.2014)
Published in 2014 IEEE 64th Electronic Components and Technology Conference (ECTC) (01.05.2014)
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Conference Proceeding
Impact of thinning stacked dies on the thermal resistance of bump-bonded three-dimensional integrated circuits
Melamed, Samson, Watanabe, Naoya, Nemoto, Shunsuke, Shimamoto, Haruo, Kikuchi, Katsuya, Aoyagi, Masahiro
Published in Microelectronics and reliability (01.12.2016)
Published in Microelectronics and reliability (01.12.2016)
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Journal Article
High-speed optical three dimensional measurement method for micro bump inspection in 3D LSI chip stacking technology
Aoyagi, Masahiro, Watanabe, Naoya, Kikuchi, Katsuya, Nemoto, Shunsuke, Arima, Noriaki, Ishizuka, Misaki, Suzuki, Koji, Shiomi, Toshio
Published in 2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) (01.12.2015)
Published in 2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) (01.12.2015)
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Conference Proceeding
Basic evaluation of Au micro-bumps formed by cyanide-free electroless Au plating process
Watanabe, Naoya, Nemoto, Shunsuke, Kikuchi, Katsuya, Aoyagi, Masahiro, Tokuhisa, Tomoaki, Owada, Takuo, Kato, Masaru
Published in 2014 IEEE 16th Electronics Packaging Technology Conference (EPTC) (01.12.2014)
Published in 2014 IEEE 16th Electronics Packaging Technology Conference (EPTC) (01.12.2014)
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Conference Proceeding
New optical three dimensional structure measurement method of cone shape micro bumps used for 3D LSI chip stacking
Aoyagi, Masahiro, Watanabe, Naoya, Suzuki, Motohiro, Kikuchi, Katsuya, Nemoto, Shunsuke, Arima, Noriaki, Ishizuka, Misaki, Suzuki, Koji, Shiomi, Toshio
Published in 2013 IEEE International 3D Systems Integration Conference (3DIC) (01.10.2013)
Published in 2013 IEEE International 3D Systems Integration Conference (3DIC) (01.10.2013)
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Conference Proceeding
Modified thermosonic flip-chip bonding based on electroplated Cu microbumps and concave pads for high-precision low-temperature assembly applications
Tung Thanh Bui, Suzuki, Motohiro, Kato, Fumiki, Watanabe, Naoya, Nemoto, Shunsuke, Kikuchi, Katsuya, Aoyagi, Masahiro
Published in 2013 IEEE 63rd Electronic Components and Technology Conference (01.05.2013)
Published in 2013 IEEE 63rd Electronic Components and Technology Conference (01.05.2013)
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Conference Proceeding
15- mu m-pitch Cu/Au interconnections relied on self-aligned low-temperature thermosonic flip-chip bonding technique for advanced chip stacking applications
Tung, Bui Thanh, Kato, Fumiki, Watanabe, Naoya, Nemoto, Shunsuke, Kikuchi, Katsuya, Aoyagi, Masahiro
Published in Japanese Journal of Applied Physics (2014)
Published in Japanese Journal of Applied Physics (2014)
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Journal Article
Wide bus chip-to-chip interconnection technology using fine pitch bump joint array for 3D LSI chip stacking
Aoyagi, M., Imura, F., Nemoto, S., Watanabe, N., Kato, F., Kikuchi, K., Nakagawa, H., Hagimoto, M., Uchida, H., Matsumoto, Y.
Published in 2012 2nd IEEE CPMT Symposium Japan (01.12.2012)
Published in 2012 2nd IEEE CPMT Symposium Japan (01.12.2012)
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Conference Proceeding
METAL NANOPARTICLE GENERATOR, AND METAL NANOPARTICLE GAS DEPOSITION APPARATUS
GOMI YOSHIHIRO, SAITO IORI, KIKUCHI KATSUYA, AOYAGI MASAHIRO, WATANABE NAOYA, NAKAGAWA HIROSHI, NEMOTO SHUNSUKE
Year of Publication 08.12.2016
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Year of Publication 08.12.2016
Patent
Developing a leading practical application for 3D IC chip stacking technology: How to progress from fundamental technology to application technology
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Published in Synthesiology (2016)
Published in Synthesiology (2016)
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METHOD FOR MANUFACTURING ELECTRONIC DEVICE
IMURA FUMITO, KIKUCHI KATSUYA, FENG WEI, AOYAGI MASAHIRO, WATANABE NAOYA, KATO FUMIKI, NAKAGAWA HIROSHI, NEMOTO SHUNSUKE
Year of Publication 26.03.2015
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Year of Publication 26.03.2015
Patent
SEMICONDUCTOR DEVICE, INTERPOSER, AND MANUFACTURING METHOD OF INTERPOSER
SAMSON MELAMED, THANH TUNG BUI, HASHINO TAKESHI, KIKUCHI KATSUYA, AOYAGI MASAHIRO, KATO FUMIKI, NAKAGAWA HIROSHI, NEMOTO SHUNSUKE
Year of Publication 24.12.2015
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Year of Publication 24.12.2015
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METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND DEVICE FOR PRODUCING SEMICONDUCTOR
BUI, THANH TUNG, MA, LAI NA, AOYAGI, MASAHIRO, WATANABE, NAOYA, SUZUKI, MOTOHIRO, KATO, FUMIKI, NEMOTO, SHUNSUKE
Year of Publication 27.03.2014
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Year of Publication 27.03.2014
Patent
Investigation of mechanism of corrosion resistance of Pd coated Cu wire joint by pseudo process
Nemoto, Shunsuke, Maeda, Takehiko, Miyajima, Masahiro, Akaike, Yasuhiko, Kitagawa, Katsuhiko, Ishii, Hideki, Shimamoto, Haruo, Kikuchi, Katsuya
Published in 2019 International Conference on Electronics Packaging (ICEP) (01.04.2019)
Published in 2019 International Conference on Electronics Packaging (ICEP) (01.04.2019)
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Conference Proceeding
Investigation into the thermal effects of thinning stacked dies in three-dimensional integrated circuits
Melamed, Samson, Watanabe, Naoya, Nemoto, Shunsuke, Kikuchi, Katsuya, Aoyagi, Masahiro
Published in 2015 21st International Workshop on Thermal Investigations of ICs and Systems (THERMINIC) (01.09.2015)
Published in 2015 21st International Workshop on Thermal Investigations of ICs and Systems (THERMINIC) (01.09.2015)
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Conference Proceeding