Efficient Realization of Table Look-Up Based Double Precision Floating Point Arithmetic
Merchant, Farhad, Choudhary, Nimash, Nandy, S. K., Narayan, Ranjani
Published in 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) (01.01.2016)
Published in 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) (01.01.2016)
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Journal Article
Hardware Solution for Real-Time Face Recognition
Mahale, Gopinath, Mahale, Hamsika, Goel, Arnav, Nandy, S. K., Bhattacharya, S., Narayan, Ranjani
Published in 2015 28th International Conference on VLSI Design (01.01.2015)
Published in 2015 28th International Conference on VLSI Design (01.01.2015)
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Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture
Krishnamoorthy, Ratna, Das, Saptarsi, Varadarajan, Keshavan, Alle, Mythri, Fujita, Masahiro, Nandy, S K, Narayan, Ranjani
Published in IPSJ Transactions on System LSI Design Methodology (2011)
Published in IPSJ Transactions on System LSI Design Methodology (2011)
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Journal Article
Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization
Merchant, Farhad, Vatwani, Tarun, Chattopadhyay, Anupam, Raha, Soumyendu, Nandy, S. K., Narayan, Ranjani
Published in IEEE transactions on parallel and distributed systems (01.08.2018)
Published in IEEE transactions on parallel and distributed systems (01.08.2018)
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Journal Article
REFRESH: REDEFINE for Face Recognition Using SURE Homogeneous Cores
Mahale, Gopinath, Mahale, Hamsika, Nandy, S. K., Narayan, Ranjani
Published in IEEE transactions on parallel and distributed systems (01.12.2016)
Published in IEEE transactions on parallel and distributed systems (01.12.2016)
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Journal Article
Router Attack toward NoC-enabled MPSoC and Monitoring Countermeasures against such Threat
Biswas, Arnab Kumar, Nandy, S. K., Narayan, Ranjani
Published in Circuits, systems, and signal processing (01.10.2015)
Published in Circuits, systems, and signal processing (01.10.2015)
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Journal Article
Applying Modified Householder Transform to Kalman Filter
Merchant, Farhad, Vatwani, Tarun, Chattopadhyay, Anupam, Raha, Soumyendu, Nandy, S K, Narayan, Ranjani, Leupers, Rainer
Published in 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID) (01.01.2019)
Published in 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID) (01.01.2019)
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Conference Proceeding
A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design
Merchant, Farhad, Vatwani, Tarun, Chattopadhyay, Anupam, Raha, Soumyendu, Nandy, S K, Narayan, Ranjani, Leupers, Rainer
Published in 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID) (01.01.2019)
Published in 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID) (01.01.2019)
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Conference Proceeding
A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths
Das, Saptarsi, Madhu, Kavitha, Krishna, Madhav, Sivanandan, Nalesh, Merchant, Farhad, Natarajan, Santhi, Biswas, Ipsita, Pulli, Adithya, Nandy, S.K., Narayan, Ranjani
Published in Journal of systems architecture (01.08.2014)
Published in Journal of systems architecture (01.08.2014)
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Journal Article
Energy aware synthesis of application kernels through composition of data-paths on a CGRA
S., Nalesh, Madhu, Kavitha T., Das, Saptarsi, Nandy, S.K., Narayan, Ranjani
Published in Integration (Amsterdam) (01.06.2017)
Published in Integration (Amsterdam) (01.06.2017)
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Journal Article
Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR)
Merchant, Farhad, Chattopadhyay, Anupam, Garga, Ganesh, Nandy, S. K., Narayan, Ranjani, Gopalan, Nandhini
Published in 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems (01.01.2014)
Published in 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems (01.01.2014)
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Conference Proceeding
Journal Article
Achieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder Transformation
Merchant, Farhad, Vatwani, Tarun, Chattopadhyay, Anupam, Raha, Soumyendu, Nandy, S. K., Narayan, Ranjani
Published in 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) (01.01.2016)
Published in 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) (01.01.2016)
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Conference Proceeding
Journal Article
Generic routing rules and a scalable access enhancement for the Network-on-Chip RECONNECT
Fell, A., Biswas, P., Chetia, J., Nandy, S.K., Narayan, R.
Published in 2009 IEEE International SOC Conference (SOCC) (01.09.2009)
Published in 2009 IEEE International SOC Conference (SOCC) (01.09.2009)
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Conference Proceeding
VOP: Architecture of a Processor for Vector Operations in On-Line Learning of Neural Networks
Mahale, Gopinath, Bhatia, Eshan, Nandy, Soumitra K., Narayan, Ranjani
Published in 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) (01.01.2016)
Published in 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) (01.01.2016)
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Conference Proceeding
Journal Article
RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels
Das, Saptarsi, Sivanandan, Nalesh, Madhu, Kavitha T., Nandy, Soumitra K., Narayan, Ranjani
Published in 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) (01.01.2016)
Published in 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) (01.01.2016)
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Conference Proceeding
Journal Article
High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit
Kala, S., Nalesh, S., Maity, Arka, Nandy, S. K., Narayan, Ranjani
Published in 2013 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2013)
Published in 2013 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2013)
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Conference Proceeding
Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations
Merchant, Farhad, Maity, Arka, Mahadurkar, Mahesh, Vatwani, Kapil, Munje, Ishan, Krishna, Madhava, Nalesh, S., Gopalan, Nandhini, Raha, Soumyendu, Nandy, S. K., Narayan, Ranjani
Published in 2015 28th International Conference on VLSI Design (01.01.2015)
Published in 2015 28th International Conference on VLSI Design (01.01.2015)
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Conference Proceeding
A Flexible Scalable Hardware Architecture for Radial Basis Function Neural Networks
Mohammadi, Mahnaz, Satpute, Nitin, Ronge, Rohit, Chandiramani, Jayesh Ramesh, Nandy, S. K., Raihan, Aamir, Verma, Tanmay, Narayan, Ranjani, Bhattacharya, Sukumar
Published in 2015 28th International Conference on VLSI Design (01.01.2015)
Published in 2015 28th International Conference on VLSI Design (01.01.2015)
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Conference Proceeding