Search Results - "NAKAGOME, YOSHINOBU" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

Review and future prospects of low-voltage RAM circuits

Review and future prospects of low-voltage RAM circuits

by Nakagome, Yoshinobu, Horiguchi, Masashi, Kawahara, Takayuki, Itoh, Kiyoo
Published in IBM journal of research and development (01.09.2003)

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Journal Article

Electron beam direct writing technology for 64-Mb DRAM LSIs

Electron beam direct writing technology for 64-Mb DRAM LSIs

by MURAI, F, NAKAYAMA, Y, SAKAMA, I, KAGA, T, NAKAGOME, Y, KAWAMOTO, Y, OKAZAKI, S
Published in Japanese Journal of Applied Physics (01.11.1990)

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Journal Article

Trends in low-power RAM circuit technologies

Trends in low-power RAM circuit technologies

by Itoh, K., Sasaki, K., Nakagome, Y.
Published in Proceedings of the IEEE (01.04.1995)

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Journal Article

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

by TAKEUCHI, KAN, NAKAGOME, YOSHINOBU
Year of Publication 28.08.2003

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Patent

New Observation of Hot-Carrier Injection Phenomena

New Observation of Hot-Carrier Injection Phenomena

by Nakagome, Yoshinobu, Takeda, Eiji, Kume, Hitoshi, Asai, Shojiro
Published in Japanese Journal of Applied Physics (01.01.1983)

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Journal Article

CMOS CIRCUIT REDUCING SWING OF SIGNAL SUITABLE FOR LOW VOLTAGE OPERATION

CMOS CIRCUIT REDUCING SWING OF SIGNAL SUITABLE FOR LOW VOLTAGE OPERATION

by ITOH KIYOO, TAKEUCHI KAN, NAKAGOME YOSHINOBU
Year of Publication 02.08.2004

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Patent

SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE

by AYUKAWA KAZUSHIGE, WATANABE TAKAO, NAKAGOME YOSHINOBU
Year of Publication 13.06.2003

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Patent

CMOS CIRCUIT CAPABLE OF REDUCING SWING OF SIGNAL

CMOS CIRCUIT CAPABLE OF REDUCING SWING OF SIGNAL

by ITOH KIYOO, TAKEUCHI KAN, NAKAGOME YOSHINOBU
Year of Publication 29.03.2003

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Patent

A Comparison of the Thermal Stabilities of Fluorinated and Hydrogenated Amorphous-Silicons

A Comparison of the Thermal Stabilities of Fluorinated and Hydrogenated Amorphous-Silicons

by Nakagome, Yoshinobu, Matsumura, Hideki, Furukawa, Seijiro
Published in Japanese Journal of Applied Physics (01.01.1980)

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Journal Article

An Amorphous-Silicon Film Usable at High-Temperature –Annealing Properties of a New Fluorinated Amorphous-Silicon

An Amorphous-Silicon Film Usable at High-Temperature –Annealing Properties of a New Fluorinated Amorphous-Silicon

by Matsumura, Hideki, Nakagome, Yoshinobu, Furukawa, Seijiro
Published in Japanese Journal of Applied Physics (01.01.1980)

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Journal Article

Memory System

Memory System

by HUNABA SEIJI, NISHIO YOJI, NAKAGOME YOSHINOBU
Year of Publication 26.09.2001

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Patent

CMOS CIRCUIT CAPABLE OF REDUCING SWING OF SIGNAL

CMOS CIRCUIT CAPABLE OF REDUCING SWING OF SIGNAL

by ITOH KIYOO, TAKEUCHI KAN, NAKAGOME YOSHINOBU
Year of Publication 15.05.2001

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Patent

SEMICONDUCTOR DEVICE WHICH IS RELATED TO LOW POWER CONSUMPTION CONTROL

SEMICONDUCTOR DEVICE WHICH IS RELATED TO LOW POWER CONSUMPTION CONTROL

by OHOKUMA SADAYUKI, NAKAMURA MASAYUKI, GAJIGAYA GAZUHIKO, NAKAGOME YOSHINOBU, HORIGUCHI MASASHI
Year of Publication 28.05.2004

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Patent

SEMICONDUCTOR DEVICE, IN WHICH POWER GENERATION CIRCUIT IS CONTROLLED TO REDUCE POWER CONSUMPTION

SEMICONDUCTOR DEVICE, IN WHICH POWER GENERATION CIRCUIT IS CONTROLLED TO REDUCE POWER CONSUMPTION

by OHOKUMA SADAYUKI, NAKAMURA MASAYUKI, GAJIGAYA GAZUHIKO, NAKAGOME YOSHINOBU, HORIGUCHI MASASHI
Year of Publication 28.05.2004

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Patent

DATA TRANSMITTER

DATA TRANSMITTER

by SATO, TAKASHI, NISHIO, YOJI, NAKAGOME, YOSHINOBU
Year of Publication 16.09.1999

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Patent

MEMORY MODULE AND DATA PROCESSING SYSTEM

MEMORY MODULE AND DATA PROCESSING SYSTEM

by SATO, TAKASHI, NISHIO, YOJI, NAKAGOME, YOSHINOBU
Year of Publication 07.01.1999

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Patent

A 1.5-ns 32-b CMOS ALU in double pass-transistor logic

A 1.5-ns 32-b CMOS ALU in double pass-transistor logic

by Suzuki, M., Ohkubo, N., Shinbo, T., Yamanaka, T., Shimizu, A., Sasaki, K., Nakagome, Y.
Published in IEEE journal of solid-state circuits (01.11.1993)

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Journal Article Conference Proceeding

Limitations and challenges of multigigabit DRAM chip design

Limitations and challenges of multigigabit DRAM chip design

by Itoh, K., Nakagome, Y., Kimura, S., Watanabe, T.
Published in IEEE journal of solid-state circuits (01.05.1997)

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Journal Article

MEMORY MODULE

MEMORY MODULE

by HUNABA SEIJI, NISHIO YOUJI, NAKAGOME YOSHINOBU, HORIGUCHI MASASHI
Year of Publication 26.09.2001

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Patent

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

by YAHATA HIDEHARU, KOKUBO MASARU, MIYASHITA HIROKI, NAKAGOME YOSHINOBU, OKUDA YUICHI
Year of Publication 15.05.2001

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Patent

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