A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques
Ha, Kyung-Soo, Lee, Seungseob, Park, Youn-Sik, Kwon, Hyuck-Joon, Oh, Tae-Young, Sohn, Young-Soo, Bae, Seung-Jun, Park, Kwang-Il, Lee, Jung-Bae, Lee, Chang-Kyo, Lee, Dongkeon, Moon, Daesik, Hwang, Hyong-Ryol, Park, Dukha, Kim, Young-Hwa, Son, Young Hoon, Na, Byongwook
Published in IEEE journal of solid-state circuits (01.01.2020)
Published in IEEE journal of solid-state circuits (01.01.2020)
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Journal Article
An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques
Lee, Chang-Kyo, Chi, Hyung-Joon, Heo, Jin-Seok, Park, Jung-Hwan, Jang, Jin-Hun, Lee, Dongkeon, Jung, Jae-Hoon, Lee, Dong-Hun, Kim, Dae-Hyun, Kim, Kihan, Kim, Sang-Yun, Park, Dukha, Lim, Youngil, Park, Geuntae, Lee, Seung-Jun, Hong, Seungki, Kwon, Dae-Hyun, Hwang, Isak, Na, Byongwook, Kim, Kyung-Ryun, Choi, Seouk-Kyu, Choi, Hyein, Hangi-Jung, Bae, Won-Il, Ihm, Jeong-Don, Bae, Seung-Jun, Kim, Nam Sung, Lee, Jung-Bae
Published in IEEE journal of solid-state circuits (01.01.2021)
Published in IEEE journal of solid-state circuits (01.01.2021)
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Journal Article
A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking
KIM, Jung-Sik, CHI SUNG OH, RYU, Jang-Woo, PARK, Kiwon, SANG KYU KANG, KIM, So-Young, KIM, Hoyoung, BANG, Jong-Min, CHO, Hyunyoon, JANG, Minsoo, HAN, Cheolmin, LEE, Jung-Bae, LEE, Hocheol, JOO SUN CHOI, JUN, Young-Hyun, LEE, Donghyuk, HYONG RYOL HWANG, HWANG, Sooman, NA, Byongwook, MOON, Joungwook, KIM, Jin-Guk, PARK, Hanna
Published in IEEE journal of solid-state circuits (2012)
Published in IEEE journal of solid-state circuits (2012)
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Conference Proceeding
Journal Article
23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power
Ha, Kyung-Soo, Lee, Chang-Kyo, Lee, Dongkeon, Moon, Daesik, Jang, Jin-Hun, Hwang, Hyong-Ryol, Chi, Hyungjoon, Park, Junghwan, Shin, Seungjun, Park, Dukha, Kim, Sang-Yun, Lim, Sukhyun, Park, Kiwon, Choi, YeonKyu, Kim, Young-Hwa, Son, Younghoon, Cho, Hyunyoon, Na, Byongwook, Ahn, Hyo-Joo, Lee, Seungseob, Choi, Seouk-Kyu, Park, Youn-Sik, Hyun, Seok-Hun, Chang, Soobong, Kwon, Hyuck-Joon, Choi, Jung-Hwan, Oh, Tae-Young, Sohn, Young-Soo, Park, Kwang-II, Jang, Seong-Jin
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
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Conference Proceeding
22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process
Chi, Hyung-Joon, Lee, Chang-Kyo, Park, Junghwan, Heo, Jin-Seok, Jung, Jaehoon, Lee, Dongkeon, Kim, Dae-Hyun, Park, Dukha, Kim, Kihan, Kim, Sang-Yun, Park, Jinsol, Cho, Hyunyoon, Lim, Sukhyun, Choi, YeonKyu, Lim, Youngil, Moon, Daesik, Park, Geuntae, Jang, Jin-Hun, Lee, Kyungho, Hwang, Isak, Kim, Cheol, Son, Younghoon, Kang, Gil-Young, Park, Kiwon, Lee, Seungjun, Doo, Su-Yeon, Shin, Chang-Ho, Na, Byongwook, Kwon, Jisuk, Kim, Kyung Ryun, Choi, Hyein, Choi, Seouk-Kyu, Chang, Soobong, Bae, Wonil, Kwon, Hyuck-Joon, Sohn, Young-Soo, Bae, Seung-Jun, Park, Kwang-Il, Lee, Jung-Bae
Published in 2020 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2020)
Published in 2020 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2020)
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Conference Proceeding
A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 \times 128 I/Os Using TSV Based Stacking
Kim, Jung-Sik, Oh, Chi Sung, Lee, Hocheol, Lee, Donghyuk, Hwang, Hyong Ryol, Hwang, Sooman, Moon, Joungwook, Kim, Jin-Guk, Park, Hanna, Ryu, Jang-Woo, Park, Kiwon, Kang, Sang Kyu, Kim, So-Young, Kim, Hoyoung, Bang, Jong-Min, Cho, Hyunyoon, Jang, Minsoo, Han, Cheolmin, LeeLee, Jung-Bae, Choi, Joo Sun, Jun, Young-Hyun
Published in IEEE journal of solid-state circuits (01.01.2012)
Published in IEEE journal of solid-state circuits (01.01.2012)
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Journal Article
A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking
Jung-Sik Kim, Chi Sung Oh, Hocheol Lee, Donghyuk Lee, Hyong-Ryol Hwang, Sooman Hwang, Byongwook Na, Joungwook Moon, Jin-Guk Kim, Hanna Park, Jang-Woo Ryu, Kiwon Park, Sang-Kyu Kang, So-Young Kim, Hoyoung Kim, Jong-Min Bang, Hyunyoon Cho, Minsoo Jang, Cheolmin Han, Jung-Bae Lee, Kyehyun Kyung, Joo-Sun Choi, Young-Hyun Jun
Published in 2011 IEEE International Solid-State Circuits Conference (01.02.2011)
Published in 2011 IEEE International Solid-State Circuits Conference (01.02.2011)
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Conference Proceeding