6.2 A 60Gb/s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ/b at 32dB Loss
LaCroix, Marc-Andre, Wong, Henry, Liu, Yun Hua, Ho, Huong, Lebedev, Semyon, Krotnev, Petar, Nicolescu, Dorin Alexandru, Petrov, Dmitry, Carvalho, Carlos, Alie, Stephen, Chong, Euhan, Musa, Faisal Ahmed, Tonietto, Davide
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
Get full text
Conference Proceeding
8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2
LaCroix, Marc-Andre, Chong, Euhan, Shen, Weilun, Nir, Ehud, Musa, Faisal Ahmed, Mei, Haitao, Mohsenpour, Mohammad-Mahdi, Lebedev, Semyon, Zamanlooy, Babak, Carvalho, Carlos, Xin, Qian, Petrov, Dmitry, Wong, Henry, Ho, Huong, Xu, Yang, Shahi, Sina Naderi, Krotnev, Peter, Feist, Chris, Huang, Howard, Tonietto, Davide
Published in 2021 IEEE International Solid- State Circuits Conference (ISSCC) (13.02.2021)
Published in 2021 IEEE International Solid- State Circuits Conference (ISSCC) (13.02.2021)
Get full text
Conference Proceeding
Modeling and Design of Multilevel Bang-Bang CDRs in the Presence of ISI and Noise
Musa, F.A., Carusone, A.C.
Published in IEEE transactions on circuits and systems. I, Regular papers (01.10.2007)
Published in IEEE transactions on circuits and systems. I, Regular papers (01.10.2007)
Get full text
Journal Article