2- TWO-LEVEL MAIN MEMORY HIERARCHY MANAGEMENT
CHEN WEI P, ALAMELDEEN ALAA R, KOZHIKKOTTU VIVEK, MURALIDHARA SAI PRASHANTH, AGARWAL RAJAT
Year of Publication 05.10.2022
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Year of Publication 05.10.2022
Patent
Reducing memory interference in multicore systems via application-aware memory channel partitioning
Muralidhara, Sai Prashanth, Subramanian, Lavanya, Mutlu, Onur, Kandemir, Mahmut, Moscibroda, Thomas
Published in 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) (01.12.2011)
Published in 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) (01.12.2011)
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Conference Proceeding
Optimizing shared cache behavior of chip multiprocessors
Kandemir, Mahmut, Muralidhara, Sai Prashanth, Narayanan, Sri Hari Krishna, Zhang, Yuanrui, Ozturk, Ozcan
Published in 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) (12.12.2009)
Published in 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) (12.12.2009)
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Conference Proceeding
Profiler and compiler assisted adaptive I/O prefetching for shared storage caches
Son, Seung Woo, Muralidhara, Sai Prashanth, Ozturk, Ozcan, Kandemir, Mahmut, Kolcu, Ibrahim, Karakoy, Mustafa
Published in 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT) (01.10.2008)
Published in 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT) (01.10.2008)
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Conference Proceeding
TWO-LEVEL MAIN MEMORY HIERARCHY MANAGEMENT
ALAA R. ALAMELDEEN, RAJAT AGARWAL, VIVEK KOZHIKKOTTU, WEI P. CHEN, SAI PRASHANTH MURALIDHARA
Year of Publication 16.06.2023
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Year of Publication 16.06.2023
Patent
A special-purpose compiler for look-up table and code generation for function evaluation
Yuanrui Zhang, Lanping Deng, Yedlapalli, Praveen, Muralidhara, Sai Prashanth, Hui Zhao, Kandemir, Mahmut, Chakrabarti, Chaitali, Pitsianis, Nikos, Xiaobai Sun
Published in 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) (01.03.2010)
Published in 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) (01.03.2010)
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Conference Proceeding
OPTIMIZED PRIORITIZATION OF MEMORY ACCESSES
Liu, Daniel, Srirangam, Narasimha Sridhar, Venkateswaran, Sharada, Hilewitz, Yedidya, Abdel Khalek, Rawan, Singh, Nishant, Witt, Wolf, Muralidhara, Sai Prashanth
Year of Publication 04.01.2024
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Year of Publication 04.01.2024
Patent
TWO-LEVEL MAIN MEMORY HIERARCHY MANAGEMENT
ALAA R. ALAMELDEEN, RAJAT AGARWAL, VIVEK KOZHIKKOTTU, WEI P. CHEN, SAI PRASHANTH MURALIDHARA
Year of Publication 06.10.2022
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Year of Publication 06.10.2022
Patent
SELECTIVE FILL FOR LOGICAL CONTROL OVER HARDWARE MULTILEVEL MEMORY
AGARWAL, Rajat, VENKATESWARAN, Sharada, MURALIDHARA, Sai Prashanth, CHEN, Wei P, LIU, Daniel W, SINGH, Nishant
Year of Publication 14.07.2022
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Year of Publication 14.07.2022
Patent
MEMORY ACCESS TRACKER IN DEVICE PRIVATE MEMORY
Kumar, Sanjay, Narayanasetty, Bhargavi, Agarwal, Rajat, Kurpad, Anupama, Voevodin, Evgeny V, Ndouniama, Patrick, Anderson, Andrew, Muralidhara, Sai Prashanth, Arafa, Mohamed
Year of Publication 23.03.2023
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Year of Publication 23.03.2023
Patent
Intra-application cache partitioning
Muralidhara, Sai Prashanth, Kandemir, Mahmut, Raghavan, Padma
Published in 2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS) (01.04.2010)
Published in 2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS) (01.04.2010)
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Conference Proceeding
TWO-LEVEL MAIN MEMORY HIERARCHY MANAGEMENT
ALAMELDEEN, Alaa R, AGARWAL, Rajat, MURALIDHARA, Sai Prashanth, CHEN, Wei P, KOZHIKKOTTU, Vivek
Year of Publication 15.07.2021
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Year of Publication 15.07.2021
Patent
MEMORY SIDE PREFETCH ARCHITECTURE FOR IMPROVED MEMORY BANDWIDTH
Moga, Adrian, Ganesh, Brinda, Kozhikkottu, Vivek, Echeruo, Ugonna, Srirangam, Narasimha Sridhar, Chinthamani, Meenakshisundaram, Roytman, Eduard, Sistla, Krishnakanth, Liu, Yen-Cheng, Alam, Hanna, Nuzman, Joseph, Muralidhara, Sai Prashanth
Year of Publication 23.03.2023
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Year of Publication 23.03.2023
Patent