A Tunnel FET for V DD Scaling Below 0.6 V With a CMOS-Comparable Performance
Asra, Ram, Shrivastava, Mayank, Murali, Kota VRM, Pandey, Rajan K, Gossner, Harald, Rao, VRamgopal
Published in IEEE transactions on electron devices (01.07.2011)
Published in IEEE transactions on electron devices (01.07.2011)
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Effect of Band-to-Band Tunneling on Junctionless Transistors
Gundapaneni, S., Bajaj, M., Pandey, R. K., Murali, K. V. R. M., Ganguly, S., Kottantharayil, A.
Published in IEEE transactions on electron devices (01.04.2012)
Published in IEEE transactions on electron devices (01.04.2012)
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Journal Article
CMOS Logic Device and Circuit Performance of Si Gate All Around Nanowire MOSFET
Nayak, Kaushik, Bajaj, Mohit, Konar, Aniruddha, Oldiges, Philip J., Natori, Kenji, Iwai, Hiroshi, Murali, Kota V. R. M., Rao, Valipe Ramgopal
Published in IEEE transactions on electron devices (01.09.2014)
Published in IEEE transactions on electron devices (01.09.2014)
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Journal Article
Metal-Gate Granularity-Induced Threshold Voltage Variability and Mismatch in Si Gate-All-Around Nanowire n-MOSFETs
Nayak, Kaushik, Agarwal, Samarth, Bajaj, Mohit, Oldiges, Philip J., Murali, Kota V. R. M., Rao, Valipe Ramgopal
Published in IEEE transactions on electron devices (01.11.2014)
Published in IEEE transactions on electron devices (01.11.2014)
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