Gate stacks for semiconductor devices of different conductivity types
Lin, Yih-Ann, Chao, Donald Y, Mor, Yi-Shien, Huang, Kuo-Tai, Chen, Ryan Chia-Jen
Year of Publication 18.06.2024
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Year of Publication 18.06.2024
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GATE-TOP DIELECTRIC STRUCTURE FOR SELF-ALIGNED CONTACT
Chen, Yi-Hsien, Li, Chung-Ting, Lin, Ta-Chun, Mor, Yi-Shien, Luo, Wen-Cheng, Chang, Chih-Hao
Year of Publication 11.01.2024
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Year of Publication 11.01.2024
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Integrated circuit structure
Mor, Yi-Shien, Liang, Chia-Ming, Chang, Chi-Hsin, Lee, Yi-Juei, Chiu, Huai-Hsien, Ng, Jin-Aun
Year of Publication 05.09.2023
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Year of Publication 05.09.2023
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Single metal that performs N work function and P work function in a high-K/metal gate
Lin, Yih-Ann, Chao, Donald Y, Mor, Yi-Shien, Huang, Kuo-Tai, Chen, Ryan Chia-Jen
Year of Publication 29.03.2022
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Year of Publication 29.03.2022
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INTEGRATED CIRCUIT STRUCTURE
LIANG, Chia-Ming, CHANG, Chi-Hsin, NG, Jin-Aun, MOR, Yi-Shien, CHIU, Huai-Hsien, LEE, Yi-Juei
Year of Publication 28.10.2021
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Year of Publication 28.10.2021
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Method of forming semiconductor structure
Mor, Yi-Shien, Liang, Chia-Ming, Chang, Chi-Hsin, Lee, Yi-Juei, Chiu, Huai-Hsien, Ng, Jin-Aun
Year of Publication 27.07.2021
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Year of Publication 27.07.2021
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Fin critical dimension loading optimization
Liang, Chia Ming, Mor, Yi-Shien, Chang, Chi-Hsin, Lee, Yi-Juei, Chiu, Huai-Hsien, Ng, Jin-Aun
Year of Publication 11.05.2021
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Year of Publication 11.05.2021
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Fin Critical Dimension Loading Optimization
Liang, Chia Ming, Mor, Yi-Shien, Chang, Chi-Hsin, Lee, Yi-Juei, Chiu, Huai-Hsien, Ng, Jin-Aun
Year of Publication 27.08.2020
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Year of Publication 27.08.2020
Patent
Fin critical dimension loading optimization
Liang, Chia Ming, Mor, Yi-Shien, Chang, Chi-Hsin, Lee, Yi-Juei, Chiu, Huai-Hsien, Ng, Jin-Aun
Year of Publication 23.06.2020
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Year of Publication 23.06.2020
Patent