An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion
BAE, Seung-Jun, PARK, Kwang-Il, BANG, Sam-Young, MOON, Gil-Shin, HWANG, Seok-Won, CHO, Young-Chul, HWANG, Sang-Jun, KIM, Dae-Hyun, LIM, Ji-Hoon, KIM, Jae-Sung, KIM, Sung-Hoon, JANG, Seong-Jin, IHM, Jeong-Don, JOO SUN CHOI, JUN, Young-Hyun, KIM, Kinam, CHO, Soo-In, SONG, Ho-Young, LEE, Woo-Jin, KIM, Hyun-Jin, KIM, Kyoung-Ho, PARK, Yoon-Sik, PARK, Min-Sang, LEE, Hong-Kyong
Published in IEEE journal of solid-state circuits (01.01.2008)
Published in IEEE journal of solid-state circuits (01.01.2008)
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Conference Proceeding
A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction
OH, Tae-Young, SOHN, Young-Soo, KIM, Jin-Hyun, KIM, Jin-Kook, KIM, Young-Sik, KIM, Byeong-Cheol, KWAK, Sang-Hyup, LEE, Jae-Hyung, LEE, Jae-Young, SHIN, Chang-Ho, YANG, Yunseok, CHO, Beom-Sig, BAE, Seung-Jun, BANG, Sam-Young, YANG, Hyang-Ja, CHOI, Young-Ryeol, MOON, Gil-Shin, PARK, Cheol-Goo, HWANG, Seok-Won, LIM, Jeong-Don, PARK, Kwang-Ii, JOO SUN CHOI, JUN, Young-Hyun, PARK, Min-Sang, LIM, Ji-Hoon, CHO, Yong-Ki, KIM, Dae-Hyun, KIM, Dong-Min, KIM, Hye-Ran, KIM, Hyun-Joong
Published in IEEE journal of solid-state circuits (01.01.2011)
Published in IEEE journal of solid-state circuits (01.01.2011)
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Journal Article
Conference Proceeding
A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW
Seung-Jun Bae, Young-Soo Sohn, Tae-Young Oh, Si-Hong Kim, Yun-Seok Yang, Dae-Hyun Kim, Sang-Hyup Kwak, Ho-Seok Seol, Chang-Ho Shin, Min-Sang Park, Gong-Heom Han, Byeong-Cheol Kim, Yong-Ki Cho, Hye-Ran Kim, Su-Yeon Doo, Young-Sik Kim, Dong-Seok Kang, Young-Ryeol Choi, Sam-Young Bang, Sun-Young Park, Yong-Jae Shin, Gil-Shin Moon, Cheol-Goo Park, Woo-Seop Kim, Hyang-Ja Yang, Jeong-Don Lim, Kwang-Il Park, Joo Sun Choi, Young-Hyun Jun
Published in 2011 IEEE International Solid-State Circuits Conference (01.02.2011)
Published in 2011 IEEE International Solid-State Circuits Conference (01.02.2011)
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Conference Proceeding
A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques
Bae, Seung-Jun, Sohn, Young-Soo, Park, Kwang-Il, Kim, Kyoung-Ho, Chung, Dae-Hyun, Kim, Jin-Gook, Kim, Si-Hong, Park, Min-Sang, Lee, Jae-Hyung, Bang, Sam-Young, Lee, Ho-Kyung, Park, In-Soo, Kim, Jae-Sung, Kim, Dae-Hyun, Kim, Hye-Ran, Shin, Yong-Jae, Park, Cheol-Goo, Moon, Gil-Shin, Yeom, Ki-Woong, Kim, Kang-Young, Lee, Jae-Young, Yang, Hyang-Ja, Jang, Seong-Jin, Choi, Joo Sun, Jun, Young-Hyun, Kim, Kinam
Published in 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers (01.02.2008)
Published in 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers (01.02.2008)
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Conference Proceeding
A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction
Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim, Dong-Min Kim, Hye-Ran Kim, Hyun-Joong Kim, Jin-Hyun Kim, Jin-Kook Kim, Young-Sik Kim, Byeong-Cheol Kim, Sang-Hyup Kwak, Jae-Hyung Lee, Jae-Young Lee, Chang-Ho Shin, Yun-Seok Yang, Beom-Sig Cho, Sam-Young Bang, Hyang-Ja Yang, Young-Ryeol Choi, Gil-Shin Moon, Cheol-Goo Park, Seok-Won Hwang, Jeong-Don Lim, Kwang-Il Park, Joo Sun Choi, Young-Hyun Jun
Published in 2010 IEEE International Solid-State Circuits Conference - (ISSCC) (01.02.2010)
Published in 2010 IEEE International Solid-State Circuits Conference - (ISSCC) (01.02.2010)
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Conference Proceeding
An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion
Ihm, Jeong-Don, Bae, Seung-Jun, Park, Kwang-Il, Song, Ho-Young, Lee, Woo-Jin, Kim, Hyun-Jin, Kim, Kyung-Ho, Lee, Ho-Kyung, Park, Min-Sang, Bang, Sam-Young, Lee, Mi-Jin, Moon, Gil-Shin, Jang, Young-Wook, Hwang, Suk-Won, Cho, Young-Chul, Hwang, Sang-Jun, Kim, Dae-Hyun, Lim, Ji-Hoon, Kim, Jae-Sung, Park, Su-Jin, Park, Ok-Joo, Yang, Se-Mi, Choi, Jin-Yong, Kim, Young-Wook, Lee, Hyun-Kyu, Kim, Sung-Hoon, Jang, Seong-Jin, Jun, Young-Hyun, Cho, Soo-in
Published in 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (01.02.2007)
Published in 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (01.02.2007)
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Conference Proceeding
METHOD OF TUNING CLOCK SIGNAL AND APPARATUS THERE-OF
MOON, GIL SHIN, PARK, KWANG IL, YEOM, KI WOONG, BAE, SEUNG JUN, BANG, SAM YOUNG
Year of Publication 13.10.2009
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Year of Publication 13.10.2009
Patent
Method and apparatus for tuning phase of clock signal
Bae, Seung Jun, Park, Kwang Il, Bang, Sam Young, Moon, Gil Shin, Yeom, Ki Woong
Year of Publication 14.08.2012
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Year of Publication 14.08.2012
Patent
Method and apparatus for tuning phase of clock signal
BAE SEUNG JUN, YEOM KI WOONG, PARK KWANG IL, BANG SAM YOUNG, MOON GIL SHIN
Year of Publication 14.08.2012
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Year of Publication 14.08.2012
Patent
Method and apparatus for tuning phase of clock signal
Bae, Seung Jun, Park, Kwang Il, Bang, Sam Young, Moon, Gil Shin, Yeom, Ki Woong
Year of Publication 08.03.2011
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Year of Publication 08.03.2011
Patent