SiGe-on-insulator symmetric lateral bipolar transistors
Yau, J.-B, Cai, J., Yoon, J., D'emic, C., Chan, K. K., Ning, T. H., Engelmann, S. U., Park, D.-G, Mo, R. T.
Published in 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (01.10.2015)
Published in 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (01.10.2015)
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Conference Proceeding
A prognostics framework for reliability optimization of mass-produced vehicle onboard diagnostics system
Fong, B., Situ, L., Poon, L. C. K., Liu, J., Mo, R. T., Tsang, K. F.
Published in 2015 IEEE 4th Global Conference on Consumer Electronics (GCCE) (01.10.2015)
Published in 2015 IEEE 4th Global Conference on Consumer Electronics (GCCE) (01.10.2015)
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Conference Proceeding
Dual stress liner enhancement in hybrid orientation technology
Sheraw, C.D., Yang, M., Fried, D.M., Costrini, G., Kanarsky, T., Lee, W.-H., Chan, V., Fischetti, M.V., Holt, J., Black, L., Naeem, M., Panda, S., Economikos, L., Groschopf, J., Kapur, A., Li, Y., Mo, R.T., Bonnoit, A., Degraw, D., Luning, S., Chidambarrao, D., Wang, X., Bryant, A., Brown, D., Sung, C.-Y., Agnello, P., Ieong, M., Huang, S.-F., Chen, X., Khare, M.
Published in Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005 (2005)
Published in Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005 (2005)
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Conference Proceeding
On the integration of CMOS with hybrid crystal orientations
Yang, M., Chan, V., Ku, S.H., Ieong, M., Shi, L., Chan, K.K., Murthy, C.S., Mo, R.T., Yang, H.S., Lehner, E.A., Surpris, Y., Jamin, F.F., Oldiges, P., Zhang, Y., To, B.N., Holt, J.R., Steen, S.E., Chudzik, M.P., Fried, D.M., Bernstein, K., Zhu, H., Sung, C.Y., Ott, J.A., Boyd, D.C., Rovedo, N.
Published in Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004 (2004)
Published in Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004 (2004)
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Conference Proceeding
High-mobility High-Ge-Content Si1−xGex-OI PMOS FinFETs with fins formed using 3D germanium condensation with Ge fraction up to x∼ 0.7, scaled EOT∼8.5Å and ∼10nm fin width
Hashemi, P., Ando, T., Balakrishnan, K., Bruley, J., Engelmann, S., Ott, J. A., Narayanan, V., Park, D.-G, Mo, R. T., Leobandung, E.
Published in 2015 Symposium on VLSI Technology (VLSI Technology) (01.06.2015)
Published in 2015 Symposium on VLSI Technology (VLSI Technology) (01.06.2015)
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Conference Proceeding
(Invited) Strained-SiGe Channel FinFETs for High-Performance CMOS: Opportunities and Challenges
Hashemi, Pouya, Balakrishnan, Karthik, Ott, John A., Leobandung, Effendi, Mo, Renee T., Park, Dae-Gyu
Published in ECS transactions (31.03.2015)
Published in ECS transactions (31.03.2015)
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Journal Article
High performance and low leakage current InGaAs-on-silicon FinFETs with 20 nm gate length
Sun, X., D'Emic, C., Cheng, C-W, Majumdar, A., Sun, Y., Cartier, E., Bruce, R. L., Frank, M., Miyazoe, H., Shiu, K-T, Lee, S., Rozen, J., Patel, J., Ando, T., Song, W-B, Lofaro, M., Krishnan, M., Obrodovic, B., Lee, K-T, Tsai, H., Wang, W-E, Spratt, W., Chan, K., Lee, S., Yau, J-B, Hashemi, P., Khojasteh, M., Cantoro, M., Ott, J., Rakshit, T., Zhu, Y., Sadana, D., Yeh, C-C, Narayanan, V., Mo, R. T., Heo, Y-C, Kim, D-W, Rodder, M. S., Leobandung, E.
Published in 2017 Symposium on VLSI Technology (01.06.2017)
Published in 2017 Symposium on VLSI Technology (01.06.2017)
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Conference Proceeding
Replacement high-K/metal-gate High-Ge-content strained SiGe FinFETs with high hole mobility and excellent SS and reliability at aggressive EOT ∼7Å and scaled dimensions down to sub-4nm fin widths
Hashemi, P., Ando, T., Balakrishnan, K., Cartier, E., Lofaro, M., Ott, J. A., Bruley, J., Lee, K.-L, Koswatta, S., Dawes, S., Rozen, J., Pyzyna, A., Chan, K., Engelmann, S. U., Park, D.-G, Narayanan, V., Mo, R. T., Leobandung, E.
Published in 2016 IEEE Symposium on VLSI Technology (01.06.2016)
Published in 2016 IEEE Symposium on VLSI Technology (01.06.2016)
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Conference Proceeding
High performance and record subthreshold swing demonstration in scaled RMG SiGe FinFETs with high-Ge-content channels formed by 3D condensation and a novel gate stack process
Hashemi, P., Ando, T., Koswatta, S., Lee, K-L, Cartier, E., Ott, J. A., Lee, C-H, Bruley, J., Lofaro, M. F., Dawes, S., Chan, K. K., Engelmann, S. U., Leobandung, E., Narayanan, V., Mo, R. T.
Published in 2017 Symposium on VLSI Technology (01.06.2017)
Published in 2017 Symposium on VLSI Technology (01.06.2017)
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Conference Proceeding
Electron mobility in thin In0.53Ga0.47As channel
Cartier, E., Majumdar, A., Lee, K-T, Ando, T., Frank, M. M., Rozen, J., Jenkins, K. A., Liang, C., Cheng, C-W, Bruley, J., Hopstaken, M., Kerber, P., Yau, J-B, Sun, X., Mo, R. T., Yeh, C-C, Leobandung, E., Narayanan, V.
Published in 2017 47th European Solid-State Device Research Conference (ESSDERC) (01.09.2017)
Published in 2017 47th European Solid-State Device Research Conference (ESSDERC) (01.09.2017)
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Conference Proceeding
(Invited) CMOS Compatible High Performance IIIV Devices: Opportunities and Challenges
Sun, Yanning, Shiu, Kuen-Ting, Cheng, Cheng-Wei, Majumdar, Amlan, Bruce, Robert, Yau, Jeng-bang, Farmer, Damon, Zhu, Yu, Hopstaken, Marinus, Frank, Martin M., Ando, Takashi, Lee, Ko-tao, Rozen, John, Sadana, Devendra K., Narayanan, Vijay, Mo, Renee T., Leobandung, Effendi
Published in ECS transactions (04.05.2016)
Published in ECS transactions (04.05.2016)
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Journal Article
Ge-on-insulator lateral bipolar transistors
Yau, J.-B, Yoon, J., Cai, J., Ning, T. H., Chan, K. K., Engelmann, S. U., Park, D.-G, Mo, R. T., Shahidi, G.
Published in 2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) (01.09.2016)
Published in 2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) (01.09.2016)
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Conference Proceeding
High-mobility High-Ge-Content Si sub(1-x)Ge sub(x)-OI PMOS FinFETs with fins formed using 3D germanium condensation with Ge fraction up to x similar to 0.7, scaled EOT similar to 8.5Aa and similar to 10nm fin width
Hashemi, P, Ando, T, Balakrishnan, K, Bruley, J, Engelmann, S, Ott, JA, Narayanan, V, Park, D-G, Mo, R T, Leobandung, E
Published in Digest of technical papers - Symposium on VLSI Technology (01.06.2015)
Published in Digest of technical papers - Symposium on VLSI Technology (01.06.2015)
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Journal Article
High Performance InGaAs Gate-All-Around Nanosheet FET on Si Using Template Assisted Selective Epitaxy
Lee, S., Cheng, C. -W., Sun, X., D'Emic, C., Miyazoe, H., Frank, M. M., Lofaro, M., Bruley, J., Hashemi, P., Ott, J. A., Ando, T., Spratt, W., Cohen, G. M., Lavoie, C., Bruce, R., Patel, J., Schmid, H., Czornomaz, L., Narayanan, V., Mo, R.T., Leobandung, E.
Published in 2018 IEEE International Electron Devices Meeting (IEDM) (01.12.2018)
Published in 2018 IEEE International Electron Devices Meeting (IEDM) (01.12.2018)
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Conference Proceeding
High-mobility high-Ge-content Si1−xGex-OI PMOS FinFETs with fins formed using 3D germanium condensation with Ge fraction up to x∼ 0.7, scaled EOT∼8.5Å and ∼10nm fin width
Hashemi, P., Ando, T., Balakrishnan, K., Bruley, J., Engelmann, S., Ott, J. A., Narayanan, V., Park, D.-G, Mo, R. T., Leobandung, E.
Published in 2015 Symposium on VLSI Circuits (VLSI Circuits) (01.06.2015)
Published in 2015 Symposium on VLSI Circuits (VLSI Circuits) (01.06.2015)
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Conference Proceeding
High-mobility high-Ge-content Si sub(1-x)Ge sub(x)-OI PMOS FinFETs with fins formed using 3D germanium condensation with Ge fraction up to x similar to 0.7, scaled EOT similar to 8.5Aa and similar to 10nm fin width
Hashemi, P, Ando, T, Balakrishnan, K, Bruley, J, Engelmann, S, Ott, JA, Narayanan, V, Park, D-G, Mo, R T, Leobandung, E
Published in 2015 Symposium on VLSI Circuits (VLSI Circuits) (01.06.2015)
Published in 2015 Symposium on VLSI Circuits (VLSI Circuits) (01.06.2015)
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Journal Article
High-performance CMOS-compatible self-aligned In0.53Ga0.47As MOSFETs with GMSAT over 2200 µS/µm at VDD = 0.5 V
Sun, Y., Majumdar, A., Cheng, C.-W, Martin, R. M., Bruce, R. L., Yau, J.-B, Farmer, D. B., Zhu, Y., Hopstaken, M., Frank, M. M., Ando, T., Lee, K.-T, Rozen, J., Basu, A., Shiu, K.-T, Kerber, P., Park, D.-G, Narayanan, V., Mo, R. T., Sadana, D. K., Leobandung, E.
Published in 2014 IEEE International Electron Devices Meeting (01.12.2014)
Published in 2014 IEEE International Electron Devices Meeting (01.12.2014)
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Conference Proceeding
On the integration of CMOS with hybrid crystal orientations
YANG, M, CHAN, V, SURPRIS, Y, JAMIN, F. F, OLDIGES, P, ZHANG, Y, TO, B. N, HOLT, J. R, STEEN, S. E, CHUDZIK, M. P, FRIED, D. M, BERNSTEIN, K, KU, S. H, ZHU, H, SUNG, C. Y, OTT, J. A, BOYD, D. C, ROVEDO, N, IEONG, M, SHI, L, CHAN, K. K, MURTHY, C. S, MO, R. T, YANG, H. S, LEHNER, E. A
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Conference Proceeding
VERFAHREN UND EINRICHTUNG ZUM ÄTZEN VON HALBLEITERWARFERN
VANDAMME, ROLAND R., ST. PETERS, MO 63376, US, ERK, HENRY F., ST. PETERS, MO 63376, US
Year of Publication 06.05.1999
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Year of Publication 06.05.1999
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