A dual core oxide 8T SRAM cell with low Vccmin and dual voltage supplies in 45nm triple gate oxide and multi Vt CMOS for very high performance yet low leakage mobile SoC applications
Ping Liu, Wang, J, Phan, M, Garg, M, Zhang, R, Cassier, A, Chua-Eoan, L, Andreev, B, Weyland, S, Ekbote, S, Han, M, Fischer, J, Yeap, Geoffrey C.-F, Ping-Wei Wang, Li, Q, Hou, C S, Lee, S B, Wang, Y F, Lin, S S, Cao, M, Mii, Y J
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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A 90-nm CMOS device technology with high-speed, general-purpose, and low-leakage transistors for system on chip applications
Wu, C.C., Leung, Y.K., Chang, C.S., Tsai, M.H., Huang, H.T., Lin, D.W., Sheu, Y.M., Hsieh, C.H., Liang, W.J., Han, L.K., Chen, W.M., Chang, S.Z., Wu, S.Y., Lin, S.S., Lin, H.C., Wang, C.H., Wang, P.W., Lee, T.L., Fu, C.Y., Chang, C.W., Chen, S.C., Jang, S.M., Shue, S.L., Lin, H.T., See, Y.C., Mii, Y.J., Diaz, C.H., Lin, B.J., Liang, M.S., Sun, Y.C.
Published in Digest. International Electron Devices Meeting (2002)
Published in Digest. International Electron Devices Meeting (2002)
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Reduced silicon donor incorporation in MBE grown GaAs layers using cracker-generated dimer arsenic
Wu, B.J., Mii, Y.J., Chen, M., Wang, K.L., Murray, J.J.
Published in Journal of crystal growth (01.05.1991)
Published in Journal of crystal growth (01.05.1991)
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Strain relaxation in Ge0.09Si0.91 epitaxial thin films measured by wafer curvature
VOLKERT, C. A, FITZGERALD, E. A, HULL, R, XIE, Y. H, MII, Y. J
Published in Journal of electronic materials (01.10.1991)
Published in Journal of electronic materials (01.10.1991)
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A new enhancement layer to improve copper interconnect performance
Hung Yi Huang, Hsieh, C H, Jeng, S M, Tao, H J, Min Cao, Mii, Y J
Published in 2010 IEEE International Interconnect Technology Conference (01.06.2010)
Published in 2010 IEEE International Interconnect Technology Conference (01.06.2010)
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Interface effect on mn-containing self-formed barrier formation with extreme low-k dielectric integration
Pan, S C, Chi, C C, Ko, C C, Kuo, H H, Huang, F M, Lee, S C, Lin, M H, Huang, H Y, Hsieh, C H, Jeng, S M, Tao, H J, Min Cao, Mii, Y J
Published in 2010 IEEE International Interconnect Technology Conference (01.06.2010)
Published in 2010 IEEE International Interconnect Technology Conference (01.06.2010)
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Cost and power/performance optimized 20nm SoC technology for advanced mobile devices
Nallapati, G., Zhu, J., Wang, J., Sheu, J. Y., Cheng, K. L., Gan, C., Yang, D., Cai, M., Cheng, J., Ge, L., Chen, Y., Bucki, R., Bowers, B., Vang, F., Chen, X., Kwon, O., Yoon, S., Wu, C. C., Chidambaram, Pr, Cao, M., Fischer, J., Terzioglu, E., Mii, Y. J., Yeap, G.
Published in 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers (01.06.2014)
Published in 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers (01.06.2014)
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28nm metal-gate high-K CMOS SoC technology for high-performance mobile applications
Yang, S. H., Sheu, J. Y., Ieong, M. K., Chiang, M. H., Yamamoto, T., Liaw, J. J., Chang, S. S., Lin, Y. M., Hsu, T. L., Hwang, J. R., Ting, J. K., Wu, C. H., Ting, K. C., Yang, F. C., Liu, C. M., Wu, I. L., Chen, Y. M., Chent, S. J., Chen, K. S., Cheng, J. Y., Tsai, M. H., Chang, W., Chen, R., Chen, C. C., Lee, T. L., Lin, C. K., Yang, S. C., Sheu, Y. M., Tzeng, J. T., Lu, L. C., Jang, S. M., Diaz, C. H., Mii, Y.
Published in 2011 IEEE Custom Integrated Circuits Conference (CICC) (01.09.2011)
Published in 2011 IEEE Custom Integrated Circuits Conference (CICC) (01.09.2011)
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High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme
Wu, C.C., Cheng, M.L., Li, T.H., Lin, Y.C., Yang, L.Y., Lin, C.P., Hou, C.S., Lin, H.C., Yang, J.L., Yu, K.F., Chen, M.J., Lin, D.W., Hsieh, T.H., Peng, Y.C., Chou, C.H., Lee, C.J., Huang, C.W., Lu, C.Y., Yang, F.K., Chen, H.K., Weng, L.W., Yen, P.C., Keshavarzi, A., Wang, S.H., Chang, S.W., Chuang, S.W., Gan, T.C., Wu, T.L., Lee, T.Y., Huang, W.S., Huang, Y.J., Tseng, Y.W., Wu, C.M., Huang, C.H., Ou-Yang, Eric, Hsu, K.Y., Lin, L.T., Wang, S.B., Kwok, T.M., Su, C.C., Tsai, C.H., Huang, M.J., Lin, H.M., Chang, A.S., Chan, C.T., Liao, S.H., Chen, L.S., Chen, J.H., Lim, P.S., Yu, X.F., Ku, S.Y., Lee, Y.B., Hsieh, P.C., Wang, P.W., Chiu, Y.H., Tseng, C.H., Lin, S.S., Tao, H.J., Cao, M., Mii, Y.J., Chen, C.L., Hsieh, C.Y., Wong, K.Y.
Published in 2010 International Electron Devices Meeting (01.12.2010)
Published in 2010 International Electron Devices Meeting (01.12.2010)
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Experimental 0.1 mu m p-channel MOSFET withp(+)-polysilicon gate on 35 A gate oxide
Taur, Y, Cohen, S, Wind, S, Lii, T, Hsu, C, Quinlan, D, Chang, C A, Buchanan, D, Agnello, P, Mii, Y-J, Reeves, C, Acovic, A, Kesan, V
Published in IEEE electron device letters (01.06.1993)
Published in IEEE electron device letters (01.06.1993)
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Experimental 0.1 mu m p-channel MOSFET with p/sup +/-polysilicon gate on 35 AA gate oxide
Taur, Y., Cohen, S., Wind, S., Lii, T., Hsu, C., Quinlan, D., Chang, C.A., Buchanan, D., Agnello, P., Mii, Y.-J., Reeves, C., Acovic, A., Kesan, V.
Published in IEEE electron device letters (01.06.1993)
Published in IEEE electron device letters (01.06.1993)
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Electrical and Physical Properties of Er-Doped HfO[sub 2] High-k Dielectrics Prepared by Atomic Layer Deposition
Wu, L., Yu, H. Y., Pey, K. L., Pan, J. S., Tuominen, M., Tois, Eva, Lee, D. Y., Hsu, K. Y., Huang, K. T., Tao, H. J., Mii, Y. J.
Published in Electrochemical and solid-state letters (2010)
Published in Electrochemical and solid-state letters (2010)
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High-k/ metal-gate stack work-function tuning by rare-earth capping layers: Interface dipole or bulk charge?
Yu, H.Y., Chang, S.Z., Aoulaiche, M., Kaczer, B., Absil, P., Adelmann, C., Hoffmann, T., Biesemans, S., Wann, C., Mii, Y.J.
Published in 2009 International Symposium on VLSI Technology, Systems, and Applications (01.04.2009)
Published in 2009 International Symposium on VLSI Technology, Systems, and Applications (01.04.2009)
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45nm SOI CMOS Technology with 3X hole mobility enhancement and Asymmetric transistor for high performance CPU application
Fung, S.K.H., Lo, H.C., Cheng, C.F., Lu, W.Y., Wu, K.C., Chen, K.H., Lee, D.H., Liu, Y.H., Wu, I.L., Li, C.T., Wu, C.H., Hsiao, F.L., Chen, T.L., Lien, W.Y., Huang, C.H., Wang, P.W., Chiu, Y.H., Lin, L.T., Chen, K.Y., Tao, H.J., Tuan, H.C., Mii, Y.J., Sun, Y.C.
Published in 2007 IEEE International Electron Devices Meeting (01.12.2007)
Published in 2007 IEEE International Electron Devices Meeting (01.12.2007)
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Novel Silicon Surface Pre-Treatment (SSPT) Technique for CMOS Device Performance Boosting
Da-Yuan Lee, Chen, C.C., Huang, C.H., Lim, P.S., Chan, M.H., Yeh, M.S., Huang, C.S., Tao, H.J., Mii, Y.J.
Published in 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) (01.04.2008)
Published in 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) (01.04.2008)
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Fully depleted 0.25 /spl mu/m MOSFETs on SOS, SIMOX and BSOI substrates
Sadana, D.K., Mii, Y.-J., Hovel, H.J., Sun, J.Y.-C., Taur, Y., Demic, C., Chan, K., Cohen, S.
Published in Proceedings. IEEE International SOI Conference (1994)
Published in Proceedings. IEEE International SOI Conference (1994)
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