A 1-MHZ bandwidth 3.6-GHz 0.18-μm CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise
MENINGER, Scott E, PERROTT, Michael H
Published in IEEE journal of solid-state circuits (01.04.2006)
Published in IEEE journal of solid-state circuits (01.04.2006)
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Conference Proceeding
Journal Article
A fractional- N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise
Meninger, S.E., Perrott, M.H.
Published in IEEE transactions on circuits and systems. 2, Analog and digital signal processing (01.11.2003)
Published in IEEE transactions on circuits and systems. 2, Analog and digital signal processing (01.11.2003)
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Journal Article