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Lightweight Structural Choices Operator for Technology Mapping
Grosnit, Antoine, Zimmer, Matthieu, Tutunov, Rasul, Li, Xing, Chen, Lei, Yang, Fan, Yuan, Mingxuan, Bou-Ammar, Haitham
Published in 2023 60th ACM/IEEE Design Automation Conference (DAC) (09.07.2023)
Published in 2023 60th ACM/IEEE Design Automation Conference (DAC) (09.07.2023)
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Prediction of Symptom-Disease Links in Online Health Forums
Gündoğan, Esra, Kaya, Buket, Kaya, Mehmet
Published in 2017 IEEE/ACM International Conference on Advances in Social Networks Analysis and Mining (ASONAM) (31.07.2017)
Published in 2017 IEEE/ACM International Conference on Advances in Social Networks Analysis and Mining (ASONAM) (31.07.2017)
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Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing
Albrecht, Christoph, Kahng, Andrew B., Mandoiu, Ion, Zelikovsky, Alexander
Published in Design Automation Conference, 7th Asia and South Pacific/ VLSI Design, 15th International Conference on (ASP-DAC/VLSI Design 2002) (07.01.2002)
Published in Design Automation Conference, 7th Asia and South Pacific/ VLSI Design, 15th International Conference on (ASP-DAC/VLSI Design 2002) (07.01.2002)
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Optimal clustering for delay minimization
Rajaraman, Rajmohan, Wong, D. F.
Published in 30th ACM/IEEE Design Automation Conference (01.07.1993)
Published in 30th ACM/IEEE Design Automation Conference (01.07.1993)
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Agent-based Fault Detection Mechanism in Wireless Sensor Networks
Shakshuki, Elhadi, Xing, Xinyu, Zhang, Haiyi
Published in Proceedings of the 2007 IEEE/WIC/ACM International Conference on Intelligent Agent Technology (02.11.2007)
Published in Proceedings of the 2007 IEEE/WIC/ACM International Conference on Intelligent Agent Technology (02.11.2007)
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Optimum design of reliable IC power networks having general graph topologies
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Boolean Technology Mapping Based on Logic Decomposition
Damiani, Maurizio, Selchenko, Andrei Y.
Published in 16th Brazilian Symposium on Integrated Circuit Design (SBCCI 2003) (08.09.2003)
Published in 16th Brazilian Symposium on Integrated Circuit Design (SBCCI 2003) (08.09.2003)
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A graph based algorithm for optimal buffer insertion under accurate delay models
Gao, Y., Wong, D.
Published in Proceedings of the conference on Design, automation and test in Europe (13.03.2001)
Published in Proceedings of the conference on Design, automation and test in Europe (13.03.2001)
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Optimal non-uniform wire-sizing under the Elmore delay model
Chen, Chung-Ping, Zhou, Hai, Wong, D. F.
Published in Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design (01.01.1997)
Published in Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design (01.01.1997)
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A technology independent block extraction algorithm
Luellau, F., Hoepken, T., Barke, E.
Published in Proceedings of the 21st Design Automation Conference (25.06.1984)
Published in Proceedings of the 21st Design Automation Conference (25.06.1984)
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