Search Results - "Masato, Motomura" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W

by Ando, Kota, Ueyoshi, Kodai, Orimo, Kentaro, Yonekawa, Haruyoshi, Sato, Shimpei, Nakahara, Hiroki, Takamaeda-Yamazaki, Shinya, Ikebe, Masayuki, Asai, Tetsuya, Kuroda, Tadahiro, Motomura, Masato
Published in IEEE journal of solid-state circuits (01.04.2018)

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Journal Article

An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA

An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA

by Ambalathankandy, Prasoon, Ikebe, Masayuki, Yoshida, Takayuki, Shimada, Takeshi, Takamaeda, Shinya, Motomura, Masato, Asai, Tetsuya
Published in IEEE transactions on circuits and systems for video technology (01.09.2020)

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Journal Article

QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS

QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS

by Ueyoshi, Kodai, Ando, Kota, Hirose, Kazutoshi, Takamaeda-Yamazaki, Shinya, Hamada, Mototsugu, Kuroda, Tadahiro, Motomura, Masato
Published in IEEE journal of solid-state circuits (01.01.2019)

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Journal Article

TT-MLP: Tensor Train Decomposition on Deep MLPs

TT-MLP: Tensor Train Decomposition on Deep MLPs

by Yan, Jiale, Ando, Kota, Yu, Jaehoon, Motomura, Masato
Published in IEEE access (01.01.2023)

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Journal Article

A GPU-Based Ising Machine With a Multi-Spin-Flip Capability for Constrained Combinatorial Optimization

A GPU-Based Ising Machine With a Multi-Spin-Flip Capability for Constrained Combinatorial Optimization

by Jimbo, Satoru, Shirai, Tatsuhiko, Togawa, Nozomu, Motomura, Masato, Kawamura, Kazushi
Published in IEEE access (2024)

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Journal Article

A Flip-count-based Dynamic Temperature Control Method for Constrained Combinatorial Optimization by Parallel Annealing Algorithms

A Flip-count-based Dynamic Temperature Control Method for Constrained Combinatorial Optimization by Parallel Annealing Algorithms

by INOUE, Genta, OKONOGI, Daiki, JIMBO, Satoru, CHU, Thiem Van, MOTOMURA, Masato, KAWAMURA, Kazushi
Published in IEICE Transactions on Information and Systems (2024)

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Journal Article

Toward Improving Ensemble-Based Collaborative Inference at the Edge

Toward Improving Ensemble-Based Collaborative Inference at the Edge

by Kumazawa, Shungo, Yu, Jaehoon, Kawamura, Kazushi, Chu, Thiem Van, Motomura, Masato
Published in IEEE access (2024)

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Journal Article

A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems

A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems

by OKONOGI, Daiki, JIMBO, Satoru, ANDO, Kota, CHU, Thiem Van, YU, Jaehoon, MOTOMURA, Masato, KAWAMURA, Kazushi
Published in IEICE Transactions on Information and Systems (01.12.2023)

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Journal Article

QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS

QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS

by Ueyoshi, Kodai, Ando, Kota, Hirose, Kazutoshi, Takamaeda-Yamazaki, Shinya, Kadomoto, Junichiro, Miyata, Tomoki, Hamada, Mototsugu, Kuroda, Tadahiro, Motomura, Masato
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01.02.2018)

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Conference Proceeding

A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers

A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers

by JIMBO, Satoru, OKONOGI, Daiki, ANDO, Kota, CHU, Thiem Van, YU, Jaehoon, MOTOMURA, Masato, KAWAMURA, Kazushi
Published in IEICE Transactions on Information and Systems (01.12.2022)

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Journal Article

Linearity Improvement of VCO-Based ADC via Complementary Bias Voltage Control for IoT Devices

Linearity Improvement of VCO-Based ADC via Complementary Bias Voltage Control for IoT Devices

by Srikram, Pitchayapatchaya, Ikebe, Masayuki, Motomura, Masato
Published in Journal of Signal Processing (01.01.2022)

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Journal Article

Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture

Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture

by Hirose, Kazutoshi, Takamaeda-Yamazaki, Shinya, Yu, Jaehoon, Motomura, Masato
Published in IEEE access (2021)

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Journal Article

Recurrent Residual Networks Contain Stronger Lottery Tickets

Recurrent Residual Networks Contain Stronger Lottery Tickets

by Garcia-Arias, Angel Lopez, Okoshi, Yasuyuki, Hashimoto, Masanori, Motomura, Masato, Yu, Jaehoon
Published in IEEE access (01.01.2023)

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Journal Article

FPGA-Based Annealing Processor with Time-Division Multiplexing

FPGA-Based Annealing Processor with Time-Division Multiplexing

by YAMAMOTO, Kasho, IKEBE, Masayuki, ASAI, Tetsuya, MOTOMURA, Masato, TAKAMAEDA-YAMAZAKI, Shinya
Published in IEICE Transactions on Information and Systems (01.12.2019)

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Journal Article

Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision

Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision

by Suzuki, Junnosuke, Yu, Jaehoon, Yasunaga, Mari, Garcia-Arias, Angel Lopez, Okoshi, Yasuyuki, Kumazawa, Shungo, Ando, Kota, Kawamura, Kazushi, Van Chu, Thiem, Motomura, Masato
Published in IEEE access (2024)

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Journal Article

An FPGA Realization of a Deep Convolutional Neural Network Using a Threshold Neuron Pruning

An FPGA Realization of a Deep Convolutional Neural Network Using a Threshold Neuron Pruning

by Fujii, Tomoya, Sato, Simpei, Nakahara, Hiroki, Motomura, Masato
Published in Applied Reconfigurable Computing (2017)

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Book Chapter

A Hardware-efficient Weight Sampling Circuit for Bayesian Neural Networks

A Hardware-efficient Weight Sampling Circuit for Bayesian Neural Networks

by Hirayama, Yuki, Asai, Tetsuya, Motomura, Masato, Takamaeda, Shinya
Published in International Journal of Networking and Computing (2020)

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Journal Article

Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation

Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation

by Marukame, Takao, Ueyoshi, Kodai, Asai, Tetsuya, Motomura, Masato, Schmid, Alexandre, Suzuki, Masamichi, Higashi, Yusuke, Mitani, Yuichiro
Published in IEEE transactions on circuits and systems. II, Express briefs (01.04.2017)

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Journal Article

Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA

Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA

by Ambalathankandy, Prasoon, Takamaeda, Shinya, Masato, Motomura, Asai, Tetsuya, Ikebe, Masayuki, Kusano, Hotaka
Published in Microprocessors and microsystems (01.09.2018)

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Journal Article

ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training

ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training

by Kumazawa, Shungo, Kawamura, Kazushi, Chu, Thiem Van, Motomura, Masato, Yu, Jaehoon
Published in International Journal of Networking and Computing (2021)

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Journal Article

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