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Development of non-Fourier thermal attitude for three-dimensional and graphene-based MOS devices
Shomali, Zahra, Abbassi, Abbas, Ghazanfarian, Jafar
Published in Applied thermal engineering (05.07.2016)
Published in Applied thermal engineering (05.07.2016)
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Complete 3D-Reduced Surface Field Superjunction Lateral Double-Diffused MOSFET Breaking Silicon Limit
Duan, Baoxing, Cao, Zhen, Yuan, Song, Yang, Yintang
Published in IEEE electron device letters (01.12.2015)
Published in IEEE electron device letters (01.12.2015)
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An Adiabatic Capacitive Artificial Neuron With RRAM-Based Threshold Detection for Energy-Efficient Neuromorphic Computing
Maheshwari, Sachin, Serb, Alexander, Papavassiliou, Christos, Prodromakis, Themistoklis
Published in IEEE transactions on circuits and systems. I, Regular papers (01.09.2022)
Published in IEEE transactions on circuits and systems. I, Regular papers (01.09.2022)
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Ferroelectric-superconductor structures properties
Pevtsov, Evgeny, Demenkova, Tatiana, Filimonov, Vladimir, Golikova, Olga
Published in Journal of physics. Conference series (01.12.2022)
Published in Journal of physics. Conference series (01.12.2022)
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Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS
Calhoun, Benton H., Cao, Yu, Li, Xin, Mai, Ken, Pileggi, Lawrence T., Rutenbar, Rob A., Shepard, Kenneth L.
Published in Proceedings of the IEEE (01.02.2008)
Published in Proceedings of the IEEE (01.02.2008)
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29.8 SHARC: Self-Healing Analog with RRAM and CNFETs
Amer, Aya G., Ho, Rebecca, Hills, Gage, Chandrakasan, Anantha P., Shulaker, Max M.
Published in Digest of technical papers - IEEE International Solid-State Circuits Conference (01.02.2019)
Published in Digest of technical papers - IEEE International Solid-State Circuits Conference (01.02.2019)
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Precharge-Free, Low-Power Content-Addressable Memory
Zackriya V., Mohammed, Kittur, Harish M.
Published in IEEE transactions on very large scale integration (VLSI) systems (01.08.2016)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.08.2016)
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Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage
Tschanz, J.W., Kao, J.T., Narendra, S.G., Nair, R., Antoniadis, D.A., Chandrakasan, A.P., De, V.
Published in IEEE journal of solid-state circuits (01.11.2002)
Published in IEEE journal of solid-state circuits (01.11.2002)
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Physically based quantum-mechanical compact model of MOS devices substrate-injected tunneling current through ultrathin (EOT similar to 1 nm) SiO sub(2) and high- Kappa gate stacks
Fei Li, Fei Li, Mudanai, S P, Fan, Yang-Yu, Register, L F, Banerjee, S K
Published in IEEE transactions on electron devices (01.01.2006)
Published in IEEE transactions on electron devices (01.01.2006)
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Design Technology Co-Optimization in advanced FDSOI CMOS around the Minimum Energy Point: body biasing and within-cell VT-mixing
Andrieu, F., Pirro, L., Berthelon, R., Morgan, J., Cibrario, G., Wiatr, M., Hoentschel, J., Vinet, M.
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Physically based quantum-mechanical compact model of MOS devices substrate-injected tunneling current through ultrathin (EOT /spl sim/ 1 nm) SiO/sub 2/ and high-/spl kappa/ gate stacks
Fei Li, Mudanai, S.P., Yang-Yu Fan, Register, L.F., Banerjee, S.K.
Published in IEEE transactions on electron devices (01.05.2006)
Published in IEEE transactions on electron devices (01.05.2006)
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Leakage current reduction in CMOS VLSI circuits by input vector control
Abdollahi, A., Fallah, F., Pedram, M.
Published in IEEE transactions on very large scale integration (VLSI) systems (01.02.2004)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.02.2004)
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