A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer
Matano, T., Takai, Y., Takahashi, T., Sakito, Y., Fujii, I., Takaishi, Y., Fujisawa, H., Kubouchi, S., Narui, S., Arai, K., Morino, M., Nakamura, M., Miyatake, S., Sekiguchi, T., Koyama, K.
Published in IEEE journal of solid-state circuits (01.05.2003)
Published in IEEE journal of solid-state circuits (01.05.2003)
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Journal Article
1.8-v 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1-Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer
FUJISAWA, Hiroki, NAKAMURA, Masayuki, ARAI, Koji, KUBOUCHI, Shuichi, FUJII, Isamu, YOKO, Hideyuki, ADACHI, Takao, TAKAI, Yasuhiro, KOSHIKAWA, Yasuji, MATANO, Tatsuya, NARUI, Seiji, USUKI, Narikazu, DONO, Chiaki, MIYATAKE, Shinichi, MORINO, Makoto
Published in IEEE journal of solid-state circuits (01.04.2005)
Published in IEEE journal of solid-state circuits (01.04.2005)
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Conference Proceeding
A multigigabit DRAM technology with 6F(2) open-bitline cell, distributed overdriven sensing, and stacked-flash fuse
Takahashi, T, Sekiguchi, T, Takemura, R, Narui, S, Fujisawa, H, Miyatake, S, Morino, M, Arai, K, Yamada, S, Shukuri, S, Nakamura, M, Tadaki, Y, Kajigaya, K, Kimura, K, Itoh, K
Published in IEEE journal of solid-state circuits (01.11.2001)
Published in IEEE journal of solid-state circuits (01.11.2001)
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Journal Article
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH INTERNAL VOLTAGE DROP CIRCUIT
TAKAHASHI, TSUTOMO, UDO, SHINJI, YOSHIOKA, HIROSHI, MORINO, MAKOTO, TAKANO, MITSUHIRO, ISHII, KYOKO, MIYATAKE, SHINICHI
Year of Publication 15.10.1999
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Year of Publication 15.10.1999
Patent
Semiconductor devices including transistors comprising a charge trapping material, and related systems and methods
Zaleski, Mark A, Morino, Makoto, Otsuka, Atsuko, Sugiura, Soichi, Fishburn, Fredrick D, Hirofuji, Keisuke, Liu, Haitao, Enomoto, Oscar O, Abe, Ichiro, Nanjo, Yoshiyuki
Year of Publication 10.11.2020
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Year of Publication 10.11.2020
Patent
SEMICONDUCTOR DEVICES INCLUDING TRANSISTORS COMPRISING A CHARGE TRAPPING MATERIAL, AND RELATED SYSTEMS AND METHODS
Zaleski, Mark A, Morino, Makoto, Otsuka, Atsuko, Sugiura, Soichi, Fishburn, Fredrick D, Hirofuji, Keisuke, Liu, Haitao, Enomoto, Oscar O, Abe, Ichiro, Nanjo, Yoshiyuki
Year of Publication 27.02.2020
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Year of Publication 27.02.2020
Patent
SEMICONDUCTOR MEMORY
MIYAKE, SUN, OKADA, TERUTAKA, MORINO, MAKOTO, NAKASHIMA, OSAMU, KAWAGUCHI, HITOSHI, YOSHIDA, MASAHIRO, YAMAGUCHI, YASUNORI, SATO, KATSUYUKI, SAEKI, TETSYA, YUKAWA, YOUSKE
Year of Publication 18.01.1996
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Year of Publication 18.01.1996
Patent
A 29-ns 64-Mb DRAM with hierarchical array architecture
Nakamura, M., Takahashi, T., Akiba, T., Kitsukawa, G., Morino, M., Sekiguchi, T., Asano, I., Komatsuzaki, K., Tadaki, Y., Songsu Cho, Kajigaya, K., Tachibana, T., Sato, K.
Published in IEEE journal of solid-state circuits (01.09.1996)
Published in IEEE journal of solid-state circuits (01.09.1996)
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Journal Article