A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS
Musah, Tawfiq, Jaussi, James, Balamurugan, Ganesh, Hyvonen, Sami, Hsueh, Tzu-Chien, Keskin, Gokce, Shekhar, Sudip, Kennedy, Joseph, Sen, Shreyas, Inti, Rajesh, Mansuri, Mozhgan, Leddige, Michael, Horine, Bryce, Roberts, Clark, Mooney, Randy, Casper, Bryan
Published in IEEE journal of solid-state circuits (01.12.2014)
Published in IEEE journal of solid-state circuits (01.12.2014)
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Journal Article
A Scalable 5-15 Gbps, 14-75 mW Low-Power I/O Transceiver in 65 nm CMOS
Balamurugan, Ganesh, Kennedy, Joseph, Banerjee, Gaurab, Jaussi, James E., Mansuri, Mozhgan, O'Mahony, Frank, Casper, Bryan, Mooney, Randy
Published in IEEE journal of solid-state circuits (01.04.2008)
Published in IEEE journal of solid-state circuits (01.04.2008)
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Journal Article
Conference Proceeding
A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS
Mansuri, Mozhgan, Jaussi, James E., Kennedy, Joseph T., Tzu-Chien Hsueh, Shekhar, Sudip, Balamurugan, Ganesh, O'Mahony, Frank, Roberts, Clark, Mooney, Randy, Casper, Bryan
Published in IEEE journal of solid-state circuits (01.12.2013)
Published in IEEE journal of solid-state circuits (01.12.2013)
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Journal Article
Conference Proceeding
A 47 × 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS
O'MAHONY, Frank, JAUSSI, James E, KENNEDY, Joseph, BALAMURUGAN, Ganesh, MANSURI, Mozhgan, ROBERTS, Clark, SHEKHAR, Sudip, MOONEY, Randy, CASPER, Bryan
Published in IEEE journal of solid-state circuits (01.12.2010)
Published in IEEE journal of solid-state circuits (01.12.2010)
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Conference Proceeding
Journal Article
Strong Injection Locking in Low- Q LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver
Shekhar, S., Balamurugan, G., Allstot, D.J., Mansuri, M., Jaussi, J.E., Mooney, R., Kennedy, J., Casper, B., O'Mahony, F.
Published in IEEE transactions on circuits and systems. I, Regular papers (01.08.2009)
Published in IEEE transactions on circuits and systems. I, Regular papers (01.08.2009)
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Journal Article
A 47 \,\times\, 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS
O'Mahony, Frank, Jaussi, James E, Kennedy, Joseph, Balamurugan, Ganesh, Mansuri, Mozhgan, Roberts, Clark, Shekhar, Sudip, Mooney, R, Casper, Bryan
Published in IEEE journal of solid-state circuits (01.12.2010)
Published in IEEE journal of solid-state circuits (01.12.2010)
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Journal Article
An 8-Gb/s simultaneous bidirectional link with on-die waveform capture
Casper, B., Martin, A., Jaussi, J.E., Kennedy, J., Mooney, R.
Published in IEEE journal of solid-state circuits (01.12.2003)
Published in IEEE journal of solid-state circuits (01.12.2003)
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Journal Article
In-situ jitter tolerance measurement technique for Serial I/O
Jaussi, J.E., Balamurugan, G., Kennedy, J., O'Mahony, F., Mansuri, M., Mooney, R., Casper, B., Un-Ku Moon
Published in 2008 IEEE Symposium on VLSI Circuits (01.06.2008)
Published in 2008 IEEE Symposium on VLSI Circuits (01.06.2008)
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Conference Proceeding
8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew
Jaussi, J.E., Balamurugan, G., Johnson, D.R., Casper, B., Martin, A., Kennedy, J., Shanbhag, N., Mooney, R.
Published in IEEE journal of solid-state circuits (01.01.2005)
Published in IEEE journal of solid-state circuits (01.01.2005)
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Journal Article
Conference Proceeding
A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS
Mansuri, M., Jaussi, J. E., Kennedy, J. T., Hsueh, T., Shekhar, S., Balamurugan, G., O'Mahony, F., Roberts, C., Mooney, R., Casper, B.
Published in 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (01.02.2013)
Published in 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (01.02.2013)
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Conference Proceeding
Future Microprocessor Interfaces: Analysis, Design and Optimization
Casper, B., Balamurugan, G., Jaussi, J.E., Kennedy, J., Mansuri, M.
Published in 2007 IEEE Custom Integrated Circuits Conference (01.09.2007)
Published in 2007 IEEE Custom Integrated Circuits Conference (01.09.2007)
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Conference Proceeding
A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS
O'Mahony, Frank, Shekhar, Sudip, Mansuri, Mozhgan, Balamurugan, Ganesh, Jaussi, James E., Kennedy, Joseph, Casper, Bryan, Allstot, David J., Mooney, Randy
Published in 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers (01.02.2008)
Published in 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers (01.02.2008)
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Conference Proceeding
SYSTEMS, METHODS, AND APPARATUSES FOR HYBRID MEMORY
CASPER BRYAN, MANSURI MOZHGAN, MOONEY RANDY, JAUSSI JAMES E, DUNNING DAVE
Year of Publication 03.09.2012
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Year of Publication 03.09.2012
Patent
26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS
Jaussi, James, Balamurugan, Ganesh, Hyvonen, Sami, Tzu-Chien Hsueh, Musah, Tawfiq, Keskin, Gokce, Shekhar, Sudip, Kennedy, Joseph, Sen, Shreyas, Inti, Rajesh, Mansuri, Mozhgan, Leddige, Michael, Horine, Bryce, Roberts, Clark, Mooney, Randy, Casper, Bryan
Published in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (01.02.2014)
Published in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (01.02.2014)
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Conference Proceeding
Analysis of PLL clock jitter in high-speed serial links
Hanumolu, P.K., Casper, B., Mooney, R., Gu-Yeon Wei, Un-Ku Moon
Published in IEEE transactions on circuits and systems. 2, Analog and digital signal processing (01.11.2003)
Published in IEEE transactions on circuits and systems. 2, Analog and digital signal processing (01.11.2003)
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Journal Article
A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems
Kennedy, J., Mooney, R., Ellis, R., Jaussi, J., Borkar, S., Jung-Hwan Choi, Jae-Kwan Kim, Chan-Kyong Kim, Woo-Seop Kim, Chang-Hyun Kim, Soo-In Cho, Loeffler, S., Hoffmann, J., Hokenmaier, W., Houghton, R., Vogelsang, T.
Published in IEEE journal of solid-state circuits (01.01.2005)
Published in IEEE journal of solid-state circuits (01.01.2005)
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Journal Article
Conference Proceeding
SYSTEMS, METHODS, AND APPARATUSES FOR HYBRID MEMORY
Mansuri, Mozhgan, Jaussi, James E, Mooney, Randy, Dunning, Dave, Casper, Bryan
Year of Publication 17.11.2021
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Year of Publication 17.11.2021
Patent
Strong injection locking of low-Q LC oscillators
Mansuri, M., O'Mahony, F., Balamurugan, G., Jaussi, J., Kennedy, J., Shekhar, S., Mooney, R., Casper, B.
Published in 2008 IEEE Custom Integrated Circuits Conference (01.09.2008)
Published in 2008 IEEE Custom Integrated Circuits Conference (01.09.2008)
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Conference Proceeding
1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS
Vivek, De, Narendra, Siva, Haycock, Matthew, Govindarajulu, Venkatesh, Erraguntla, Vasantha, Wilson, Howard, Vangal, Sriram, Pangal, Amaresh, Seligman, Erik, Nair, Raj, Keshavarzi, Ali, Bloechel, Bradley, Dermer, Gregory, Mooney, Randy, Borkar, Nitin, Borkar, Shekhar
Published in Digest of technical papers - IEEE International Solid-State Circuits Conference (01.01.2002)
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Published in Digest of technical papers - IEEE International Solid-State Circuits Conference (01.01.2002)
Journal Article