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"MOLSON PHILIPPE"
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"MOLSON PHILIPPE"
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Finite impulse response (FIR) filter compiler
by
MOLSON PHILIPPE
,
SAN TONY
Year of Publication
19.09.2006
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Patent
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Finite impulse response (FIR) filter compiler
by
San, Tony
,
Molson
,
Philippe
Year of Publication
19.09.2006
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23
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Hardware opencore evaluation
by
Molson
,
Philippe
,
San, Tony
Year of Publication
08.08.2006
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24
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Hardware opencore evaluation
by
MOLSON PHILIPPE
,
SAN TONY
Year of Publication
08.08.2006
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Automated Generation of Hardware Accelerators with Direct Memory Access from ANSI/ISO Standard C Functions
by
Lau, D.
,
Pritchard, O.
,
Molson, P.
Published in
2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
(01.04.2006)
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Conference Proceeding
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26
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DSP design system level power estimation
by
PEQUILLAT FRANCOIS
,
PLOFSKY JORDAN
,
MOLSON PHILIPPE
Year of Publication
01.02.2011
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27
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DSP design system level power estimation
by
Plofsky, Jordan
,
Molson
,
Philippe
,
Pequillat, Francois
Year of Publication
01.02.2011
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28
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Method and apparatus for enabling waveform display in a system design model
by
MOLSON PHILIPPE
Year of Publication
15.04.2008
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29
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Method and apparatus for enabling waveform display in a system design model
by
Molson
,
Philippe
Year of Publication
15.04.2008
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30
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High-level language code sequence optimization for implementing programmable chip designs
by
LAU DAVID JAMES
,
BALL JAMES L
,
KEMPA JESSE
,
MOLSON PHILIPPE
,
PRITCHARD JEFFREY ORION
,
BLACKBURN JARROD COLIN JAMES
Year of Publication
03.05.2016
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31
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Scheduling optimization of aliased pointers for implementation on programmable chips
by
LAU DAVID JAMES
,
MOLSON PHILIPPE
,
PRITCHARD JEFFREY ORION
Year of Publication
16.10.2012
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32
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Scheduling optimization of aliased pointers for implementation on programmable chips
by
Lau, David James
,
Pritchard, Jeffrey Orion
,
Molson
,
Philippe
Year of Publication
16.10.2012
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33
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Method and apparatus for simulating a hybrid system with registered and concurrent nodes
by
RIGGS ADAM SCHOTT
,
MOLSON PHILIPPE
Year of Publication
20.02.2007
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34
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Method and apparatus for simulating a hybrid system with registered and concurrent nodes
by
Riggs, Adam Schott
,
Molson
,
Philippe
Year of Publication
20.02.2007
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35
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Interleaver-deinterleaver megacore
by
Molson
,
Philippe
,
San, Tony
Year of Publication
14.10.2003
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36
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Interleaver-deinterleaver megacore
by
MOLSON PHILIPPE
,
SAN TONY
Year of Publication
14.10.2003
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37
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System level simulation models for hardware modules
by
MOLSON PHILIPPE
,
FOX JEFFREY R
,
SAN TONY
Year of Publication
24.03.2009
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System level simulation models for hardware modules
by
Molson
,
Philippe
,
San, Tony
,
Fox, Jeffrey R
Year of Publication
24.03.2009
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39
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High-level language code sequence optimization for implementing programmable chip designs
by
LAU DAVID JAMES
,
BALL JAMES L
,
KEMPA JESSE
,
MOLSON PHILIPPE
,
PRITCHARD JEFFREY ORION
,
BLACKBURN JARROD COLIN JAMES
Year of Publication
05.11.2013
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DSP design system level power estimation
by
PEQUILLAT FRANCOIS
,
PLOFSKY JORDAN
,
MOLSON PHILIPPE
Year of Publication
28.11.2006
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